Senior Lead Verification Architect – FPGA/SoC

Altera Corporation; San Jose (CA); Presencial; USD 232.000 - 330.000; Jornada completa

Ventajas ofrecidas por este puesto de trabajo

Incentive opportunities

Descripción de la vacante

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verification of FPGA, programmable SoC, and platform solutions. You will shape verification architecture, drive coverage-driven closure, and lead cross-functional teams to ensure silicon and product readiness.

You will define scalable verification strategies, develop reusable environments, and mentor engineers while collaborating with RTL design, CAD, emulation, firmware, and validation

Formación

• Bachelor’s degree plus 15+ years in design verification for FPGA/ASIC/SoC.
• Deep SystemVerilog/UVM expertise with coverage-driven closure.

Responsabilidades

• Lead verification architecture, planning, and execution for complex FPGA, SoC, and infrastructure subsystems.
• Define verification plans translating architecture into measurable objectives.
• Architect scalable verification environments and scoreboards; drive coverage closure.
• Advance verification methodology, coding standards, and regression practices across programs.
• Drive verification closure with functional, code, assertions, and cross-coverage; manage risk and readiness.
• Collaborate with architecture, RTL, CAD, emulation, firmware, and validation teams.

Conocimientos

SystemVerilog

UVM

Constrained-random verification

Assertions

Coverage-driven verification

Verification IP

Mentoring

Cross-functional collaboration

Educación

Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science

Herramientas

UVM framework

Python

Descripción del empleo

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verification of FPGA, programmable SoC, and platform solutions. You will shape verification architecture, drive coverage-driven closure, and lead cross-functional teams to ensure silicon and product readiness.

You will define scalable verification strategies, develop reusable environments, and mentor engineers while collaborating with RTL design, CAD, emulation, firmware, and validation