Senior Lead Verification Architect — FPGA/SoC

191 Altera Corporation; San Jose (CA); Vor Ort; USD 232.000 - 330.000; Vollzeit

Benefits dieser Stelle

Incentives based on performance

Zusammenfassung

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands‑on technical leadership for verification of FPGA, SoC, and platform solutions. You will shape verification architecture, develop reusable environments, and drive coverage‑driven closure from architecture to silicon.

The role requires deep SystemVerilog/UVM expertise, strong judgment, and the ability to influence engineering execution across global teams.

Qualifikationen

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or related discipline.
• 15+ years of relevant experience in design verification for FPGA, ASIC, SoC, or semiconductor products.

Aufgaben

• Lead verification architecture, planning, and execution for complex FPGA, SoC, and subsystems.
• Define verification plans translating requirements into functional, performance, and coverage objectives.
• Architect/develop scalable SystemVerilog/UVM environments, IP, scoreboards, and coverage models.
• Advance verification methodology, coding standards, testbench guidelines, and regression practices.
• Drive verification closure using functional, code, assertions, and cross coverage; assess risks and readiness.

Kenntnisse

SystemVerilog

UVM

Verification leadership

Verification architecture

Constrained-random verification

Testbench architecture

Regression management

Cross-functional collaboration

Debug and root-cause analysis

Ausbildung

Electrical Engineering degree

Tools

C/C++

SystemC

Python

Tcl

Jobbeschreibung

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands‑on technical leadership for verification of FPGA, SoC, and platform solutions. You will shape verification architecture, develop reusable environments, and drive coverage‑driven closure from architecture to silicon.

The role requires deep SystemVerilog/UVM expertise, strong judgment, and the ability to influence engineering execution across global teams.