Senior Lead Engineer - Design Verification

Altera; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera in San Jose, California is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verifying FPGA, SoC, and platform solutions from architecture through silicon. You will shape verification strategy, develop reusable environments, and drive coverage-driven closure.

This senior individual-contributor role requires deep SystemVerilog/UVM expertise, strong judgment, and the ability to influence across global teams.

Qualifications

• 15+ years in design verification for FPGA/ASIC/SoC.
• Leadership delivering verification from architecture to RTL and beyond.
• Deep expertise in SystemVerilog and UVM with coverage-driven closure.
• Experience creating reusable verification IP and methodologies.
• Experience in high-performance digital architectures.

Responsibilities

• Lead verification architecture, planning, and execution for complex subsystems, including block, subsystem, and full-chip verification.
• Define verification plans translating architectural intent into measurable objectives.
• Architect and develop scalable SystemVerilog/UVM environments, verification IP, scoreboards, and coverage models.
• Advance methodology, coding standards, testbench guidelines, and regression practices.
• Drive verification closure, identify coverage gaps, and assess risk until exit criteria are met.
• Partner with architecture and RTL design teams to clarify specs and resolve issues.
• Lead debug of difficult simulation, integration, and system-level failures with root-cause analysis.
• Develop and maintain scalable simulation, regression, build, and reporting infrastructure.
• Collaborate with emulation, FPGA prototyping, CAD, firmware, software, and post-silicon teams.
• Provide mentorship and verification leadership through reviews and hands-on guidance.

Skills

SystemVerilog/UVM expertise

Verification leadership

Constrained-random verification

Reusable VIP/UVSM

Testbench architecture

Education

Bachelor's degree + 15+ years experience

Tools

UVM frameworks

Simulation tooling

Job description

About the Role

Altera is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for the verification of next-generation FPGA, programmable SoC, and platform solutions. This senior individual-contributor role will shape verification architecture, methodology, and execution for complex digital subsystems and full-chip integrations. In this role, you will define scalable verification strategies, develop reusable verification environments, and drive coverage-driven closure from early architecture through silicon and product readiness. The successful candidate combines deep SystemVerilog/UVM expertise with strong technical judgment, a high bar for verification quality, and the ability to influence engineering execution across global, cross-functional teams.

Responsibilities

• Lead verification architecture, planning, and execution for complex FPGA, programmable SoC, and infrastructure-class subsystems, including block, subsystem, and full-chip verification.
• Define comprehensive verification plans that translate architectural intent and product requirements into measurable functional, performance, resilience, and coverage objectives.
• Architect and develop scalable, reusable SystemVerilog/UVM verification environments, verification IP, scoreboards, reference models, constrained-random stimulus, checkers, and coverage models.
• Establish and advance verification methodology, coding standards, testbench guidelines, regression practices, and automation that improve consistency, quality, reuse, debug efficiency, and predictability across programs.
• Drive verification closure using functional, code, assertion, and cross coverage; identify coverage gaps, evaluate risk, and ensure readiness against defined exit criteria.
• Partner closely with architecture and RTL design teams to clarify specifications, identify verification risks early, review microarchitecture, and resolve complex functional or performance issues.
• Lead debug of difficult simulation, integration, and system-level failures; apply rigorous root-cause analysis and drive timely resolution across design, verification, firmware, and validation teams.
• Develop and maintain scalable simulation, regression, build, and reporting infrastructure to support efficient development and release quality.
• Collaborate with emulation, FPGA prototyping, physical design, CAD, firmware, software, board, and post-silicon teams to ensure verification intent is carried through implementation, bring-up, and product delivery.
• Provide technical mentorship and verification leadership through methodology reviews, test-plan reviews, code reviews, and hands-on guidance to engineers across the organization.

What You Will Bring

You are a hands-on verification leader who combines deep technical expertise with a practical, systems-level perspective. You bring disciplined engineering judgment, a collaborative leadership style, and a passion for building the verification foundations that enable Altera to deliver differentiated, high-quality programmable solutions.

Salary Range

The pay range below is for Bay Area California only. Actual salary may vary based on a number of factors including job location, job-related knowledge, skills, experiences, trainings, etc. We also offer incentive opportunities that reward employees based on individual and company performance.

$231,500 - $330,000 USD

We use artificial intelligence to screen, assess, or select applicants for the position. Applicants must be eligible for any required U.S. export authorizations.

Minimum Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, Computer Science, or a related technical discipline, with 15+ years of relevant experience in design verification for FPGA, ASIC, SoC, or semiconductor products; advanced degree preferred.
• Demonstrated technical leadership delivering verification for complex digital subsystems or products from architecture through RTL verification, integration, full-chip verification, and hardware or silicon validation.
• Deep expertise in SystemVerilog and UVM, including constrained-random verification, assertions, self-checking environments, testbench architecture, functional coverage, and coverage-driven closure.
• Proven experience creating reusable verification IP, UVM frameworks, testbench components, or methodology adopted across multiple blocks, teams, or programs.
• Experience verifying high-performance digital architectures such as networking or packet-processing datapaths, memory subsystems, on-chip interconnect, PCIe/CXL, Ethernet, high-speed I/O, or programmable acceleration.
• Strong understanding of RTL design, microarchitecture, simulation, debug, formal or static verification concepts, and hardware development flows.
• Experience with regression management, simulation build and execution flows, test automation, and data-driven verification reporting.
• Demonstrated ability to collaborate and influence across architecture, RTL design, CAD, emulation, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills, with the ability to clearly communicate verification strategy, risk, closure status, and technical recommendations to diverse audiences.

Preferred Qualifications

• Experience verifying FPGA architectures, programmable-logic devices, configurable interconnect, SmartNICs, IPUs, SoCs, or data-center acceleration platforms.
• Experience with C/C++, SystemC, Python, Tcl, Perl, or shell scripting for reference models, automation, testbench infrastructure, or verification productivity.
• Experience with formal verification, low-power verification, CDC/RDC analysis, performance verification, or hardware-accelerated verification environments.
• Experience with full-chip verification, processor-based test development, firmware/software co-verification, or post-silicon debug.
• Experience leading verification methodology or mentoring engineers in a matrixed engineering environment.
• A record of innovation through patents, publications, standards contributions, or sustained methodology leadership.

Job Type

Regular

Shift

Shift 1 (United States of America)

Primary Location

San Jose, California, United States

Posting Statement

All qualified applicants will receive consideration for employment without regard to race, color, religion, religious creed, sex, national origin, ancestry, age, physical or mental disability, medical condition, genetic information, military and veteran status, marital status, pregnancy, gender, gender expression, gender identity, sexual orientation, or any other characteristic protected by local law, regulation, or ordinance.