Senior RTL Design Lead — FPGA/SoC Architect

Altera Corporation; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera Corporation seeks a Senior Lead Design Engineer - RTL Design in San Jose, CA to drive RTL architecture and implementation for FPGA/SoC platforms. You will own critical blocks, guide architecture, verification, and post-silicon readiness, while mentoring teams across global engineering groups.

You translate requirements into scalable microarchitectures, set clocking strategies, and push high-performance, power-efficient designs with a focus on quality, timing, and schedule.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related field; 15+ years in FPGA/ASIC/SoC product development.
• Leadership delivering complex digital designs from architecture through post-silicon.
• Deep expertise in Verilog and SystemVerilog RTL development, synthesis, lint, CDC/RDC, timing constraints.
• Experience with high-performance digital subsystems such as PCIe/CXL, Ethernet, memory subsystems.

Responsibilities

• Lead RTL architecture and microarchitecture for complex FPGA/SoC subsystems.
• Own RTL design for critical blocks and subsystem integrations.
• Define design specs, timing constraints, and implementation plans across teams.
• Drive tradeoffs among throughput, latency, power, area, timing, and schedule.
• Mentor teams and advance RTL design methodologies.

Skills

RTL design leadership

Verilog/SystemVerilog

FPGA/SoC architecture

Mentorship

Cross-functional collaboration

Education

Bachelor’s degree in Electrical/Computer Engineering

15+ years in FPGA/ASIC/SoC development

Tools

Verilog

SystemVerilog

Synthesis

Lint/CDCs

Formal/Equivalence checking

PCIe/CXL

Job description

Altera Corporation seeks a Senior Lead Design Engineer - RTL Design in San Jose, CA to drive RTL architecture and implementation for FPGA/SoC platforms. You will own critical blocks, guide architecture, verification, and post-silicon readiness, while mentoring teams across global engineering groups.

You translate requirements into scalable microarchitectures, set clocking strategies, and push high-performance, power-efficient designs with a focus on quality, timing, and schedule.