Senior Lead Verification Architect - FPGA/SoC

Altera; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera in San Jose, California is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verifying FPGA, SoC, and platform solutions from architecture through silicon. You will shape verification strategy, develop reusable environments, and drive coverage-driven closure.

This senior individual-contributor role requires deep SystemVerilog/UVM expertise, strong judgment, and the ability to influence across global teams.

Qualifications

• 15+ years in design verification for FPGA/ASIC/SoC.
• Leadership delivering verification from architecture to RTL and beyond.
• Deep expertise in SystemVerilog and UVM with coverage-driven closure.
• Experience creating reusable verification IP and methodologies.
• Experience in high-performance digital architectures.

Responsibilities

• Lead verification architecture, planning, and execution for complex subsystems, including block, subsystem, and full-chip verification.
• Define verification plans translating architectural intent into measurable objectives.
• Architect and develop scalable SystemVerilog/UVM environments, verification IP, scoreboards, and coverage models.
• Advance methodology, coding standards, testbench guidelines, and regression practices.
• Drive verification closure, identify coverage gaps, and assess risk until exit criteria are met.
• Partner with architecture and RTL design teams to clarify specs and resolve issues.
• Lead debug of difficult simulation, integration, and system-level failures with root-cause analysis.
• Develop and maintain scalable simulation, regression, build, and reporting infrastructure.
• Collaborate with emulation, FPGA prototyping, CAD, firmware, software, and post-silicon teams.
• Provide mentorship and verification leadership through reviews and hands-on guidance.

Skills

SystemVerilog/UVM expertise

Verification leadership

Constrained-random verification

Reusable VIP/UVSM

Testbench architecture

Education

Bachelor's degree + 15+ years experience

Tools

UVM frameworks

Simulation tooling

Job description

Altera in San Jose, California is seeking a Senior Lead Engineer - Design Verification to provide hands-on technical leadership for verifying FPGA, SoC, and platform solutions from architecture through silicon. You will shape verification strategy, develop reusable environments, and drive coverage-driven closure.

This senior individual-contributor role requires deep SystemVerilog/UVM expertise, strong judgment, and the ability to influence across global teams.