Senior RTL Design Lead — FPGA & SoC Architect

Altera; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership across RTL architecture, design, integration, and delivery for next-generation FPGA and programmable SoC solutions. This role combines technical leadership with individual contribution across global engineering teams.

You will drive design specifications, timing, verification alignment, and collaboration with verification, physical design, firmware, and software teams to ensure successful

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or related technical discipline.
• Demonstrated hands-on RTL design leadership from architecture to post-silicon validation.
• Strong Verilog/SystemVerilog RTL development, synthesis, lint, and timing constraints.

Responsibilities

• Lead RTL architecture and implementation for FPGA/SoC subsystems focusing on high-throughput datapaths.
• Own RTL blocks and subsystems, ensuring reusable, synthesizable, scalable, and testable code.

Skills

Verilog/SystemVerilog

RTL design and implementation

Synthesis and lint

CDC/RDC and timing constraints

Architecture and microarchitecture

Board/firmware/software collaboration

Python/Tcl scripting

Leadership and mentorship

Education

Bachelor’s degree in Electrical/Computer Engineering or related

Advanced degree preferred

Job description

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands-on technical leadership across RTL architecture, design, integration, and delivery for next-generation FPGA and programmable SoC solutions. This role combines technical leadership with individual contribution across global engineering teams.

You will drive design specifications, timing, verification alignment, and collaboration with verification, physical design, firmware, and software teams to ensure successful