Senior RTL Architect for FPGA & SoC Solutions

191 Altera Corporation; San Jose (CA); Presencial; USD 232.000 - 330.000; Jornada completa

Descripción de la vacante

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands‑on technical leadership for RTL architecture, design, integration, and delivery of FPGA and programmable SoC solutions in San Jose, California.

You will translate system requirements into robust microarchitectures, guide execution from concept to RTL delivery, and mentor engineers while maintaining high quality, performance, and power targets.

Formación

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical discipline, with 15+ years of relevant experience in FPGA, ASIC, SoC, or semiconductor product development, advanced degree preferred.
• Deep hands‑on expertise in Verilog and/or SystemVerilog RTL development, synthesis, lint, CDC/RDC, formal or equivalence checking, timing constraints, and implementation‑aware design practices.
• Proven experience designing high‑performance digital subsystems, such as network or data‑processing pipelines, memory controllers or memory subsystems, on‑chip interconnect, traffic‑management logic, PCIe/CXL, Ethernet, high‑speed interfaces, or programmable acceleration engines.
• Strong understanding of architectural and RTL‑level tradeoffs involving bandwidth, latency, congestion, buffering, throughput, power, area, timing, and reliability.
• Experience leading design execution across multiple functional blocks or complex subsystem integration, including technical planning, risk management, schedule alignment, and prioritization.
• Demonstrated ability to collaborate and influence across architecture, design verification, physical design, DFT, CAD, firmware/software, system validation, and product engineering organizations.
• Strong written and verbal communication skills, with the ability to clearly communicate design intent, technical risks, and recommended solutions to diverse audiences.

Responsabilidades

• Lead RTL architecture, microarchitecture, and implementation for complex FPGA, programmable SoC, and infrastructure‑class subsystems, with emphasis on high‑throughput datapaths, memory access, interconnect, packet or data processing, and programmable acceleration.
• Own RTL design for critical blocks and subsystem integrations, ensuring code is reusable, synthesizable, scalable, testable, and aligned to performance, power, area, and timing objectives.
• Define design specifications, interface contracts, clocking and reset strategies, performance targets, and implementation plans that align architecture, verification, physical design, firmware, software, and product requirements.
• Drive technical tradeoffs across throughput, latency, bandwidth, buffering, power, area, timing, reliability, scalability, cost, and schedule; identify and mitigate architectural and execution risks early.
• Establish and advance RTL design methodologies, including coding standards, lint, CDC/RDC, synthesis, formal checks, automation, and design‑review practices that improve engineering quality and predictability.
• Partner with design verification to shape verification strategy, review test plans and coverage, triage failures, and drive efficient closure of complex pre‑silicon issues.
• Collaborate with physical design, CAD, DFT, emulation, FPGA prototyping, board, firmware, software, and post‑silicon teams to preserve RTL intent through implementation, timing closure, validation, and product delivery.
• Lead root‑cause analysis and resolution of complex design, integration, performance, and system‑level issues using disciplined debug and data‑driven decision‑making.
• Provide technical mentorship and RTL leadership across teams; raise the engineering bar through architecture reviews, RTL/code reviews, and constructive guidance to senior and developing engineers.
• Influence design roadmaps and collaborate with internal teams and external partners on reusable IP, EDA capabilities, and implementation approaches that strengthen Altera’s programmable technology portfolio.

Conocimientos

RTL design leadership

Verilog/SystemVerilog

High‑level digital design

Cross‑functional collaboration

Educación

Bachelor's degree in Electrical Engineering, Computer Engineering, or a related technical discipline

Advanced degree preferred

Herramientas

RTL synthesis

Scripting/EDA tools

Formal/checking tools

Descripción del empleo

Altera is seeking a Senior Lead Design Engineer - RTL Design to provide hands‑on technical leadership for RTL architecture, design, integration, and delivery of FPGA and programmable SoC solutions in San Jose, California.

You will translate system requirements into robust microarchitectures, guide execution from concept to RTL delivery, and mentor engineers while maintaining high quality, performance, and power targets.