Senior Lead FPGA/SoC Architect & Tech Leader

191 Altera Corporation; San Jose (CA); On-site; USD 232,000 - 330,000; Full time

Job summary

Altera is seeking a Senior Lead Design Engineer in San Jose to provide hands-on technical leadership across FPGA, programmable SoC, and infrastructure-class subsystems. You will drive architecture, RTL design, verification, and post-silicon readiness, translating complex product requirements into scalable, high-performance digital solutions.

You will mentor teams, define interfaces, and collaborate with architecture, CAD, firmware, and software groups to ensure architectural integrity and timely

Qualifications

• Bachelor’s degree in Electrical Engineering or related field.
• 15+ years of experience in FPGA/ASIC/SoC or semiconductor product development.
• Proven leadership delivering complex digital subsystems from architecture through post-silicon.

Responsibilities

• Lead architecture, microarchitecture, and RTL development for FPGA, SoC, and subsystems.
• Define requirements, interfaces, and implementation plans aligning hardware, firmware, software, and validation.
• Drive tradeoffs across performance, power, area, latency, and schedule; mitigate execution risk.
• Own critical blocks through RTL to post-silicon validation and bring-up.
• Establish reusable IP, coding standards, and quality methodologies to improve velocity and predictability.
• Collaborate across architecture, RTL, verification, physical design, CAD, firmware, and software teams.

Skills

RTL design

SystemVerilog

FPGA architecture

Digital subsystems

Leadership

Cross-functional collaboration

Education

Electrical Engineering degree

Advanced degree preferred

Tools

Python scripting

Synthesis tools

Job description

Altera is seeking a Senior Lead Design Engineer in San Jose to provide hands-on technical leadership across FPGA, programmable SoC, and infrastructure-class subsystems. You will drive architecture, RTL design, verification, and post-silicon readiness, translating complex product requirements into scalable, high-performance digital solutions.

You will mentor teams, define interfaces, and collaborate with architecture, CAD, firmware, and software groups to ensure architectural integrity and timely