Senior IP Logic Designer - RTL & SoC Integration (Hybrid)

Intel Corporation; Santa Clara (CA); Hybride; USD 164 000 - 232 000; Plein temps

Résumé du poste

Intel Corporation in Santa Clara, CA seeks an IP Logic Design Engineer to develop high-quality RTL IP blocks for integration into full chip designs. You will optimize power, performance, and area, and collaborate across teams to ensure successful IP-to-SoC handoffs.

The role requires strong RTL design, SystemVerilog expertise, and experience with AMBA/IP coherence protocols, with a hybrid on-site/remote work model and a competitive compensation package.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related STEM field with 6+ years of RTL design and SystemVerilog OR Master's degree in relevant field with 4+ years of RTL design and SystemVerilog
• Industry-standard tools for front-end design, including synthesis, STA, and lint checks
• AMBA protocols and coherent protocols such as IDI or CHI
• Hardware design concepts such as logic design, state machines, and network-on-chip architectures

Responsabilités

• Develop logic designs, RTL coding, and simulation for IP blocks and subsystems for integration into full chip designs
• Define architecture and microarchitecture features and ensure their implementation in the design
• Optimize design logic to meet power, performance, area, and timing goals while maintaining physical implementation integrity
• Review verification plans and address RTL test failures to ensure accurate validation of design features
• Collaborate with physical design teams to address floorplan limitations and integrate designs seamlessly
• Drive quality assurance compliance to enable smooth IP-to-SoC handoff

Connaissances

RTL design

SystemVerilog

Cross-functional collaboration

Attention to detail

Formation

Bachelor's or Master's in a related STEM field

Electrical/Computer Engineering or Computer Science

Outils

Synthesis

Static Timing Analysis (STA)

Lint checks

AMBA protocols

IDI/CHI coherence protocols

Description du poste

Intel Corporation in Santa Clara, CA seeks an IP Logic Design Engineer to develop high-quality RTL IP blocks for integration into full chip designs. You will optimize power, performance, and area, and collaborate across teams to ensure successful IP-to-SoC handoffs.

The role requires strong RTL design, SystemVerilog expertise, and experience with AMBA/IP coherence protocols, with a hybrid on-site/remote work model and a competitive compensation package.