AI SoC Microarchitecture Design Engineer

Intel Corporation; Folsom (CA); On-site; USD 164,000 - 312,000; Full time

Benefits offered by this job

Stock bonuses

Health benefits

Vacation

Job summary

Intel Corporation in Santa Clara, CA, seeks an experienced engineer to drive RTL design and verification for next-generation SoCs. The role emphasizes SystemVerilog, microarchitecture, and secure design practices within a fast-paced environment.

You will define architecture, validate IP integration, and ensure timing, power, and area targets are met, collaborating across multidisciplinary teams to deliver high-quality silicon on schedule.

Qualifications

• Bachelor's degree in Electrical Engineering, Computer Engineering, Computer Science, or a related field.
• Experience with microarchitecture, RTL design, coding, and simulation using SystemVerilog.
• Strong knowledge of system-level design principles including power, performance, and area optimization.
• Demonstrated experience with timing/power convergence methodologies and tools.

Responsibilities

• Develop logic design, RTL coding, and simulation for SoC designs.
• Define and implement architecture and microarchitecture features for logic blocks.
• Perform quality checks across RTL, timing, power, and design integrity to meet performance goals.
• Optimize RTL logic to ensure compliance with power, performance, area, and timing targets.
• Collaborate with IP providers to integrate and validate IPs at the SoC level.
• Review and contribute to verification plans and ensure design features are comprehensively tested.
• Identify and resolve RTL test failures to ensure feature correctness.
• Employ secure development practices to address security objectives and threats in the design.
• Drive quality assurance compliance for seamless IP and SoC handoff throughout the design flow.

Skills

SystemVerilog

RTL design

microarchitecture

timing convergence

power/area optimization

Education

Bachelors in Electrical/Computer Engineering or related

Job description

Intel Corporation in Santa Clara, CA, seeks an experienced engineer to drive RTL design and verification for next-generation SoCs. The role emphasizes SystemVerilog, microarchitecture, and secure design practices within a fast-paced environment.

You will define architecture, validate IP integration, and ensure timing, power, and area targets are met, collaborating across multidisciplinary teams to deliver high-quality silicon on schedule.