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eInfochips Inc is seeking an experienced SOC/IP Integration Engineer to lead RTL design and complex SoC integration efforts. The role covers 1P/3P IP integration, fabric generation, quality checks, and PD handoff.
You will work with Verilog/SystemVerilog, run synthesis, manage timing constraints, and support floorplanning for performance optimization, ensuring design-quality closure. Candidates should have 5–7 years of related experience with a 4-year degree, or 3 years plus an advanced degree.
eInfochips Inc is seeking an experienced SOC/IP Integration Engineer to lead RTL design and complex SoC integration efforts. The role covers 1P/3P IP integration, fabric generation, quality checks, and PD handoff.
You will work with Verilog/SystemVerilog, run synthesis, manage timing constraints, and support floorplanning for performance optimization, ensuring design-quality closure. Candidates should have 5–7 years of related experience with a 4-year degree, or 3 years plus an advanced degree.