Principal Logic Design Engineer - San Jose

Cypress HCM; San Francisco (CA); Hybrid; USD 180,000 - 240,000; Full time

Benefits offered by this job

Medical benefits

401K with company match

Employee stock purchase plan

ESOP discount

Job summary

Cypress HCM is seeking an experienced RTL design lead for ASIC/FPGA developments in a hybrid San Jose, CA Hillsboro, OR area. You will drive architecture decisions, mentor teams, and collaborate across verification, implementation, and customer engagements.

The role requires 8+ years of logic design, expertise in Verilog/SystemVerilog and UVM, and strong memories/interfaces knowledge. A BSEE or MSEE is preferred, with competitive benefits and stock options.

Qualifications

• 8+ years of logic design experience in ASIC/FPGA development.
• Proficiency in Verilog/SystemVerilog RTL design and UVM-based verification environments.
• Background in high-speed memory or interface technologies.

Responsibilities

• Lead RTL design and microarchitecture development for complex digital logic blocks.
• Drive architecture decisions through performance, power, and area analysis.
• Partner with verification teams to improve test strategies and coverage.
• Collaborate with implementation teams to resolve design timing and power challenges.
• Debug and resolve design issues identified during verification and validation.
• Support technical discussions during customer evaluations and engagements.
• Assist with product integration and deployment activities.

Skills

RTL design

SystemVerilog

Verilog

UVM verification

Performance analysis

Timing closure

Python scripting

TCL scripting

Memory interfaces

Collaboration & leadership

Education

BSEE

MSEE

Tools

Questas

Incisive

VCS

Verilog

SystemVerilog

Python

TCL

Job description

Location: San Jose, CA 95134 or Hillsboro, OR 97006 | Hybrid Remote: 3 days in the office per week

Responsibilities

• Leading RTL design and microarchitecture development for complex digital logic blocks
• Drive architecture decisions through performance, power, and area analysis
• Partner with verification teams to improve test strategies and coverage
• Collaborate with implementation teams to resolve design, timing, and power challenges
• Debug and resolve design issues identified during verification and validation
• Support technical discussions during customer evaluations and engagements
• Assist with product integration and deployment activities

Requirements

• 8+ years of logic design experience – ASIC and/or FPGA development
• Expertise in Verilog/SystemVerilog RTL design and UVM-based verification environments
• Background in high-speed memory or interface technologies
• Experience with industry-standard simulation and verification tools (Questa, Incisive, VCS)
• Proficiency in scripting languages such as Python, Perl, or TCL
• Experience with synthesis, static timing analysis, and clock/reset domain methodologies
• Experience with on-chip interconnects and industry-standard protocols
• Exposure to advanced SoC or high-performance computing designs
• BSEE and/or MSEE (preferred)
• Competitive medical, dental, vision, and life insurance plans – including HSA and FSA options
• 401K plan with company match
• Employee stock purchase plan (15% discount)