Senior SoC Integration Engineer (RTL & IP)

Apple Inc.; Santa Clara, Northern (CA, KY); Hybrid; USD 185,000 - 325,000; Full time

Benefits offered by this job

Stock programs

Discretionary bonuses

Relocation assistance

Comprehensive medical & dental

Job summary

Apple Inc. in Santa Clara, CA, is seeking a senior hardware engineer to join a team crafting next‑gen SoCs. You will integrate IP blocks, manage RTL codebases, and define top-level interconnects for complex hardware solutions.

The role emphasizes experience with SystemVerilog/Verilog, and SoC design flows, working with ASIC tool chains, linting, and timing constraints to achieve robust designs.

Qualifications

• Bachelor's degree with 10+ years in hardware/SoC design.
• Solid RTL development experience using SystemVerilog and Verilog.
• Familiarity with bus protocols AXI, AHB, APB and interfaces PCIe/USB/DDR.
• Knowledge of ASIC tool flows: lint, synthesis, CDC, DFT, STA.

Responsibilities

• IP Integration: integrate third-party or internal IP blocks into a SoC.
• RTL Integration: merge RTL codebases and ensure AMBA/AXI/AHB interface correctness.
• Top-Level Assembly: create and maintain top-level SoC RTL and interconnects.
• Linting and Synthesis: run lint and synthesis; resolve CDC/RDC issues.
• Build and Test Infrastructure: develop automated build/regression for integration.

Skills

Digital logic design

RTL development

SystemVerilog

Verilog

SoC design flows

Synopsys

Cadence

AXI

AHB

APB

PCIe

USB

DDR

Debugging

Communication

Education

Bachelor's Degree +10+ years

Tools

Lint

Synthesis

CDC

DFT

STA

Job description

Apple Inc. in Santa Clara, CA, is seeking a senior hardware engineer to join a team crafting next‑gen SoCs. You will integrate IP blocks, manage RTL codebases, and define top-level interconnects for complex hardware solutions.

The role emphasizes experience with SystemVerilog/Verilog, and SoC design flows, working with ASIC tool chains, linting, and timing constraints to achieve robust designs.