SoC IP & RTL Integration Engineer

Apple Inc.; Santa Clara (CA); Hybrid; USD 150,000 - 278,000; Full time

Benefits offered by this job

Comprehensive medical and dental

Retirement benefits

Discounted products and free services

Educational expense reimbursement

Relocation assistance

Job summary

Apple Inc. in Santa Clara, California is seeking a dedicated hardware engineer to join its SoC RTL team. You will integrate IP blocks, manage RTL codebases, and help deliver silicon powering Apple’s hardware products.

Responsibilities include integration, synthesis, timing closure, verification support, and design reviews. A strong background in SystemVerilog, AXI/AHB, and SoC design flows is required, with collaborative, cross-functional skills.

Qualifications

• Solid understanding of digital logic design and RTL development using SystemVerilog/Verilog.
• Familiarity with SoC design flows and tools (Synopsys, Cadence).
• Experience with bus protocols (AXI, AHB, APB) and interface standards (PCIe, USB, DDR).
• Knowledge of ASIC tool flows: lint, synthesis, CDC, DFT, STA.

Responsibilities

• IP Integration: Integrate third-party or internal IP blocks into a SoC.
• RTL Integration: Merge RTL codebases and ensure bus/interface protocols are implemented.
• Top-Level Assembly: Create and maintain top-level SoC RTL, wrappers, and interconnects.
• Linting and Synthesis: Run and debug lint, CDC/RDC, and logic synthesis.

Skills

SystemVerilog

RTL design

SoC design flows

Education

Bachelor's Degree with +3 Years of Experience

Tools

Synopsys

Cadence

Job description

Apple Inc. in Santa Clara, California is seeking a dedicated hardware engineer to join its SoC RTL team. You will integrate IP blocks, manage RTL codebases, and help deliver silicon powering Apple’s hardware products.

Responsibilities include integration, synthesis, timing closure, verification support, and design reviews. A strong background in SystemVerilog, AXI/AHB, and SoC design flows is required, with collaborative, cross-functional skills.