Senior IC Packaging Engineer: NPI & Failure Analysis

NVIDIA; Santa Clara (CA); On-site; USD 216,000 - 345,000; Full time

Job summary

NVIDIA in Santa Clara, CA is seeking an experienced engineer to lead rapid IC packaging development for FA and NPI, coordinating with internal teams and external foundries to meet tight turnaround, reliability, and chip–package interaction goals.

This role requires 12+ years in IC packaging, deep flip-chip and 2.5D/3D packaging knowledge, and hands-on use of Cadence Allegro Package Designer; strong FA tooling skills (SEM, EDX, CSAM, X-ray) and cross‑functional collaboration.

Qualifications

• B.S., M.S., or Ph.D. in a materials science, mechanical, electrical, physics or related semiconductor field.
• Deep packaging expertise in flip-chip, 2.5D/3D packaging, wire bonding, and advanced substrate architectures.
• 12+ years hands-on experience in IC packaging development and/or NPI.
• Experience with IC package EDA software (Cadence Allegro Package Designer) and FEM tools (ANSYS/ABAQUS).
• FA tooling proficiency: SEM, EDX, CSAM, X-Ray, and LIT.

Responsibilities

• Drive the process, mechanical, thermal, and material evaluation of the latest IC packages.
• Manage rapid prototyping builds, package stack-ups, and assembly processes for FA and NPI use cases.
• Coordinate comprehensive physical and electrical failure analysis on prototype builds, reliability-tested components to determine root causes.
• Collaborate with IC & Package design teams, process & product engineering; coordinate with foundries and OSAT partners to develop and test required processes, tooling, and workflows.

Skills

IC packaging

NPI experience

Failure analysis

Cross-functional

Education

B.S./M.S./Ph.D. in related semiconductor field

Tools

Cadence Allegro Package Designer; ANSYS; ABAQUS; SEM; EDX; CSAM; X-Ray; LIT

Job description

NVIDIA in Santa Clara, CA is seeking an experienced engineer to lead rapid IC packaging development for FA and NPI, coordinating with internal teams and external foundries to meet tight turnaround, reliability, and chip–package interaction goals.

This role requires 12+ years in IC packaging, deep flip-chip and 2.5D/3D packaging knowledge, and hands-on use of Cadence Allegro Package Designer; strong FA tooling skills (SEM, EDX, CSAM, X-ray) and cross‑functional collaboration.