Senior Packaging Engineer - Chip Pad Ring & Interconnect

2100 NVIDIA USA; California (MO); On-site; USD 168,000 - 322,000; Full time

Job summary

NVIDIA in California is seeking an experienced engineer to define and implement the chip pad ring, substrate interconnect scheme, and to lead the package layout design process across complex silicon packages.

You will work with circuit, SI, RTL, place-and-route, substrate layout and system design teams, shaping a robust world-class electrical package while communicating clearly across the organization.

Qualifications

• BSEE or equivalent experience.
• 8+ years in board/system design; package design experience preferred.
• Good understanding of transmission line theory, power delivery and signal integrity.
• Perl, Python, Tcl scripting; Cadence skills and Excel familiarity are a plus.
• Hardworking and able to work with a minimum of supervision.
• You seek to solve complex technical problems.

Responsibilities

• Define and implement the chip pad ring, substrate interconnect scheme, and lead the package layout design process.
• Collaborate with Circuit, Signal Integrity, RTL, Place and Route, substrate layout and system design Engineers and Managers.
• Work to define a chip floor plan, pad ring, substrate, and ball out implementing a robust world-class electrical package.
• Communicate effectively with various teams throughout the company

Skills

Python

Perl

Tcl

Signal integrity

Power delivery

Education

BSEE or equivalent experience

Tools

Cadence

Excel

Job description

NVIDIA in California is seeking an experienced engineer to define and implement the chip pad ring, substrate interconnect scheme, and to lead the package layout design process across complex silicon packages.

You will work with circuit, SI, RTL, place-and-route, substrate layout and system design teams, shaping a robust world-class electrical package while communicating clearly across the organization.