Senior Package Layout Engineer: High‑Speed ASIC Packaging

Nvidia Corporation in

Santa Clara (CA)

On-site

USD 130,000 - 180,000

Full time

11 days ago

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Job summary

NVIDIA is seeking a Senior Package Layout Engineer for Hardware to design and optimize complex IC substrates for GPUs and SOCs. You will work with design teams to plan schedules, resolve manufacturing and electrical design issues, and contribute to high-density package solutions.

Responsibilities include substrate layout, pinout optimization, and developing CAD libraries using Cadence tools to enhance layout productivity.

Qualifications

  • BS in Electrical Engineering or equivalent.
  • 5+ years of PCB layout experience for graphics cards, motherboards, line cards or related technology.
  • Experience with HDI designs is a plus.
  • Proven experience in substrate layout of wire bond and flip chip packages is preferred.

Responsibilities

  • Collaborate to implement high speed/density ASIC packages.
  • Perform substrate breakout patterns for ASIC packages.
  • Optimize package pinout with system-level trade-offs of pins assignment.
  • Help perform package routing, placement, stack-up, reference plane and power distribution using Cadence APD or SiP tool suite.
  • Propose layout design trade-offs to the Technical Package Lead for resolution and implementation.
  • Conduct design feasibility studies to evaluate the Package design goals for size, cost, and system performance.
  • Develop symbols and CAD library databases using Cadence APD design tools
  • Develop methodologies to improve layout productivity

Skills

PCB Layout
HDI designs
Wire bond/flip chip

Education

BS in Electrical Engineering

Tools

Cadence APD
SiP tool suite

Job description

NVIDIA is seeking a Senior Package Layout Engineer for Hardware to design and optimize complex IC substrates for GPUs and SOCs. You will work with design teams to plan schedules, resolve manufacturing and electrical design issues, and contribute to high-density package solutions.

Responsibilities include substrate layout, pinout optimization, and developing CAD libraries using Cadence tools to enhance layout productivity.

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