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NVIDIA is seeking an experienced Engineer to lead rapid IC packaging development for FA and NPI in Santa Clara, CA. You will drive R&D with internal and external partners, and establish advanced packaging processes to meet turnaround, reliability, and chip-package interaction goals.
The role requires 12+ years in IC packaging, deep knowledge of flip-chip, 2.5D/3D packaging, and familiarity with EDA tools like Cadence Allegro and FEM software (ANSYS/ABAQUS). Equity and benefits are included.
We are looking for an experienced Engineer who will lead the development of rapid IC packaging of individual die, to enable Failure Analysis and NPI tasks ahead of high-volume manufacturing. This will include planning & driving related R&D with multiple internal and external partners and you will be responsible for establishing advanced packaging processes needed to meet our NPI goals regarding packaging turn‑around‑time, reliability, and chip‑package interaction. Prior knowledge of Package related Failure Analysis is beneficial.
Compensation includes a base salary range of 168,000 USD - 270,250 USD for Level 5 and 216,000 USD - 345,000 USD for Level 6, depending on location, experience, and comparable positions. You will also be eligible for equity and benefits.
Applications will be accepted until July 19, 2026.
NVIDIA uses AI tools in its recruiting processes.
NVIDIA is committed to fostering an inclusive work environment and proud to be an equal opportunity employer. As we highly value diversity in our current and future employees, we do not discriminate (including in our hiring and promotion practices) on the basis of race, religion, color, national origin, gender, gender expression, sexual orientation, age, marital status, veteran status, disability status or any other characteristic protected by law.