Senior IC Layout Designer

Micron Technology; Boise (ID); On-site; USD 120,000 - 180,000; Full time

Benefits offered by this job

Health insurance

Dental plan

Vision plan

Paid time off

Paid holidays

Job summary

Micron Technology, a world leader in memory and storage solutions, seeks a Senior Layout Designer to develop multi-dimensional layouts and detailed drawings from schematics. You will verify data integrity and lead major block developments across global sites, mentoring junior engineers and driving layout automation.

Ideal candidates bring 5+ years in semiconductor layout, strong CAD/EDA tool proficiency, and excellent communication skills to collaborate with TD, design, and CAD teams worldwide.

Qualifications

• AS or Bachelor’s in Electronics, Electrical Engineering, or related field with 5+ years in semiconductor layout design.
• Strong working knowledge of EDA tools (Cadence Virtuoso, Synopsys, Calibre).
• Proven ability to debug problems via root-cause analysis and collaborate with engineering staff.
• Skilled in developing layout, floor-planning, signal-planning and power-planning methodologies.
• Excellent verbal and written communication skills; understanding of design rules and layout quality.

Responsibilities

• Organize and prioritize logistics and resources to meet deadlines.
• Contribute to group management and technical innovation.
• Assign resources, schedule tasks, and deliver quality-controlled results.
• Contribute to projects in a globally distributed design/layout environment.
• Mentor junior team members and drive layout automation improvements.
• Lead major blocks and product revisions with strong planning.

Skills

Root-cause analysis

Layout design

Cross-functional communication

Debugging

CAD/EDA methodologies

Education

Bachelor's degree in Electronics or Electrical Engineering

Tools

Cadence Virtuoso

Synopsys

Calibre

Job description

Micron Technology, a world leader in memory and storage solutions, seeks a Senior Layout Designer to develop multi-dimensional layouts and detailed drawings from schematics. You will verify data integrity and lead major block developments across global sites, mentoring junior engineers and driving layout automation.

Ideal candidates bring 5+ years in semiconductor layout, strong CAD/EDA tool proficiency, and excellent communication skills to collaborate with TD, design, and CAD teams worldwide.