Senior GPU RTL Power Engineer — Power-Efficient IP

Bzpp

United States

Presencial

USD 124.000 - 186.000

Jornada completa

14 días+

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Ventajas ofrecidas por este puesto de trabajo

Medical insurance
Dental insurance
Vision coverage
Life insurance
401(k) plan
Onsite lunch
Tuition assistance
Paid time off
Student loan program
Wellness incentives

Descripción de la vacante

Samsung Austin research and development centers seek a Senior GPU RTL Power Engineer to optimize power for mobile GPU IPs. You will partner with hardware, software, and system teams to implement RTL-level and microarchitectural power optimization techniques across multiple GPU generations.

The role involves clock gating, voltage scaling, and low-power modes to balance performance, power, and area, with opportunities to influence architecture and documentation across projects.

Formación

  • 2+ years of experience in GPU/CPU architecture and RTL power optimization.
  • Strong understanding of RTL power analysis and optimization.
  • Proficiency in SystemVerilog and ASIC design flow.
  • Scripting skills in Python or Perl.
  • Experience with clock gating and low-power techniques.

Responsabilidades

  • Contribute to RTL/microarchitecture power optimization strategy.
  • Collaborate with RTL, performance, modelling, and validation teams.
  • Implement power-saving techniques to deliver differentiated IP designs.
  • Document methodologies, strategy, results, and best practices.
  • Stay ahead of GPU technologies and explore new power optimization approaches.

Conocimientos

GPU architecture
RTL power analysis
SystemVerilog
Python/Perl
PPA tradeoffs
Power optimization
Debugging

Educación

Bachelor's degree in CS/CE or related

Herramientas

PowerArtist
PTPX
Empower

Descripción del empleo

Samsung Austin research and development centers seek a Senior GPU RTL Power Engineer to optimize power for mobile GPU IPs. You will partner with hardware, software, and system teams to implement RTL-level and microarchitectural power optimization techniques across multiple GPU generations.

The role involves clock gating, voltage scaling, and low-power modes to balance performance, power, and area, with opportunities to influence architecture and documentation across projects.

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