Senior FPGA Design Engineer – Memory Test Systems

LitePoint; San Jose (CA); On-site; USD 170,000 - 273,000; Full time

Benefits offered by this job

Health benefits

Retirement savings plans

Paid vacation and holidays

Tuition assistance programs

Job summary

Teradyne's Memory Test Division seeks a Senior FPGA Design Engineer to develop cutting-edge memory test solutions. You will architect FPGA designs, guide junior engineers, and translate customer needs into robust, scalable hardware.

The role emphasizes RTL-focused development, timing analysis, and tool-flow expertise, with occasional travel and a base salary range reflecting experience and location.

Qualifications

• BS or MS in Electrical Engineering or closely related discipline with 8+ years of relevant work experience.
• Experience with Digital Design and Architecture, RTL coding, timing closure and lab validation.
• Experience with Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Experience with C or C++ and lab equipment (oscilloscopes, power supplies, waveform generators).

Responsibilities

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers.
• Turn abstract concepts and customer requirements into reliable, extensible designs.
• Assist in maintenance and extension of existing FPGA designs to support quality improvement.
• Maintain schedule commitments and deliver high quality end products.
• Occasional travel may be required.

Skills

Digital Design & Architecture

RTL coding

Static Timing Analysis

Digital simulation testbench

C/C++

Lab equipment familiarity

Education

B.S. or M.S. in Electrical Engineering

Tools

Intel/Xilinx FPGA tool flows

Job description

Teradyne's Memory Test Division seeks a Senior FPGA Design Engineer to develop cutting-edge memory test solutions. You will architect FPGA designs, guide junior engineers, and translate customer needs into robust, scalable hardware.

The role emphasizes RTL-focused development, timing analysis, and tool-flow expertise, with occasional travel and a base salary range reflecting experience and location.