FPGA Engineering Manager - Memory Test & RTL Lead

Teradyne; Tualatin (OR); On-site; USD 171,000 - 273,600; Full time

Benefits offered by this job

Health and well‑being benefits

Medical insurance

Dental insurance

Vision insurance

Retirement savings plan

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.

You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.

Qualifications

• 12+ years in Digital ASIC or FPGA design.
• 5+ years as FPGA/ASIC project lead, driving multiple projects.
• Experience coding RTL (Verilog).
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Proficient in Vivado/Quartus tools.

Responsibilities

• Plan and manage multiple FPGA projects to on-time delivery.
• Represent FPGA team on core teams and program reviews.
• Provide support for sustaining issues.
• Collaborate with hardware, software, and firmware for integration.
• Recruit, onboard, and retain engineers to build a high-performing team.
• Set goals and conduct performance conversations for 4–6 engineers.
• Contribute to FPGA process improvement initiatives.
• Provide hands-on guidance on architectures, designs, and specs.
• Participate in RTL coding, synthesis, timing closure, and lab validation.

Skills

RTL Verilog

STA tools

PCIe

DDR3/4/5

AXI

SERDES

Vivado/Quartus

UVM

Git/CI

Education

B.S./M.S. in Electrical Engineering

Tools

Cadence

Vivado

Quartus

Lint

CDC

Git

CI pipelines

Job description

Teradyne's Memory Test Division in Tualatin, OR is seeking an experienced FPGA Engineering Manager to lead a small team and deliver advanced memory test solutions, combining digital and analog design with PCIe, DDR, and SERDES interfaces.

You will plan multiple FPGA projects, mentor 4–6 engineers, collaborate across hardware, software, and firmware, and drive architectural reviews, RTL coding, and lab validation to ensure on-time delivery.