Senior FPGA Design Engineer for Memory Test Systems

LitePoint; Tualatin (OR); On-site; USD 155,000 - 248,000; Full time

Benefits offered by this job

Health and well-being benefit programs

Job summary

Teradyne in Oregon seeks a Senior FPGA Design Engineer to advance memory test instrumentation. You will architect FPGA solutions for Flash and DRAM, guide junior engineers, and translate customer requirements into robust, scalable designs.

The role also involves maintaining existing FPGA code and delivering high-quality products on schedule. Requires 8+ years in electrical engineering with strong RTL/Verilog, timing analysis, lab validation, C/C++, and familiarity with lab equipment.

Qualifications

• must have B.S. or M.S. in Electrical Engineering with 8+ years of relevant work experience
• experience with Digital Design and Architecture
• RTL coding, synthesis, timing closure and lab validation
• Static Timing Analysis of ASICs or FPGAs
• experience with digital simulation testbench creation
• experience with C or C++
• familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators

Responsibilities

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers
• Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
• Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
• Maintain schedule commitments and deliver high quality end products.
• Occasional travel may be required.

Job description

Teradyne in Oregon seeks a Senior FPGA Design Engineer to advance memory test instrumentation. You will architect FPGA solutions for Flash and DRAM, guide junior engineers, and translate customer requirements into robust, scalable designs.

The role also involves maintaining existing FPGA code and delivering high-quality products on schedule. Requires 8+ years in electrical engineering with strong RTL/Verilog, timing analysis, lab validation, C/C++, and familiarity with lab equipment.