Lead FPGA Engineering Manager: Drive Next-Gen Memory Tests

Teradyne; San Jose (CA); On-site; USD 171,000 - 273,600; Full time

Job summary

Teradyne is seeking an FPGA Engineering Manager in San Jose to lead the development of memory test solutions. You will oversee multiple FPGA projects, guide RTL design and validation, and drive timely delivery with a high-performing team of 4–6 engineers.

You will collaborate with cross-functional groups to ensure seamless integration of FPGA designs into systems and contribute to process improvements while mentoring engineers and handling recruitment.

Qualifications

• B.S. or M.S. in Electrical Engineering or closely related discipline.
• 12+ years of relevant experience in Digital ASIC or FPGA design.
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects.
• Extensive experience coding RTL (Verilog preferred).
• Extensive experience using digital simulation tools (Cadence preferred).
• Extensive experience using static timing analysis tools.
• Experience designing with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with AMD or Altera FPGAs and development tools (Vivado/Quartus).
• Experience using digital design quality tools such as Lint, CDC.

Responsibilities

• Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope.
• Represent the FPGA team on project core teams and at program reviews.
• Provide support for sustaining issues.
• Work closely with cross-functional teams, including hardware, software, and firmware engineers, to ensure seamless integration of FPGA designs into larger systems.
• Recruit, onboard, and retain top engineering talent to build a high-performing team.
• Set goals and conduct regular performance conversations for a team of 4 to 6 engineers.
• Contribute to FPGA team process improvement initiatives.
• Provide hands-on technical guidance to the FPGA engineering team, including reviewing and contributing to FPGA architectures, designs, and specifications.
• Actively participate in FPGA design and development, including RTL coding, synthesis, timing closure, and lab validation.

Skills

RTL coding

Cadence tools

Static timing analysis

PCIe

DDR4/5

AXI

Verilog

FPGA Design Leadership

Verilog/SystemVerilog

Education

B.S. or M.S. in Electrical Engineering

Related discipline

Tools

Vivado

Quartus

Job description

Teradyne is seeking an FPGA Engineering Manager in San Jose to lead the development of memory test solutions. You will oversee multiple FPGA projects, guide RTL design and validation, and drive timely delivery with a high-performing team of 4–6 engineers.

You will collaborate with cross-functional groups to ensure seamless integration of FPGA designs into systems and contribute to process improvements while mentoring engineers and handling recruitment.