Memory Test FPGA Engineering Manager - Lead & Deliver

Teradyne; San Jose (CA); On-site; USD 171,000 - 273,600; Full time

Job summary

Teradyne is seeking an experienced FPGA Engineering Manager to lead a team developing cutting-edge memory test solutions. You will oversee RTL/FPGA design, coordinate with hardware/software/firmware groups, and ensure timely delivery of high-quality products.

The role requires a strong background in Digital ASIC/FPGA design, leadership of 4–6 engineers, and hands-on participation in RTL coding and lab validation. Competitive salary and discretionary bonuses accompany challenging projects.

Qualifications

• B.S. or M.S. in Electrical Engineering or closely related discipline required.
• 12+ years of relevant experience in Digital ASIC or FPGA design.
• Minimum of 5 years of experience as an FPGA/ASIC project lead, driving multiple projects through concept development, architectural exploration, design implementation, lab validation, and production release.
• Extensive experience coding RTL (Verilog preferred).
• Extensive experience using digital simulation tools (Cadence preferred).
• Extensive experience using static timing analysis tools.
• Experience designing with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with AMD or Altera FPGAs and development tools (Vivado/Quartus).
• Experience with digital design quality tools e.g. Lint, CDC.
• Experience with bug tracking tools and source control systems/CI.
• Familiarity with digital verification tools and methodologies (preferably UVM).
• Excellent presentation and communication skills.

Responsibilities

• Plan, prioritize, and manage multiple FPGA development projects, ensuring on-time delivery within budget and scope.
• Represent the FPGA team on project core teams and at program reviews.
• Provide support for sustaining issues.
• Collaborate with hardware, software, and firmware teams to integrate FPGA designs into larger systems.
• Recruit, onboard, and retain top engineering talent for a high-performing team.
• Set goals and conduct performance conversations for a team of 4 to 6 engineers.
• Contribute to FPGA team process improvement initiatives.
• Provide hands-on technical guidance on FPGA architectures, designs, and specifications.
• Participate in FPGA design and development including RTL coding, synthesis, timing closure, and lab validation.

Skills

RTL coding (Verilog)

Digital ASIC/FPGA design

FPGA/ASIC project lead

Digital verification (UVM)

Communication skills

Lab validation

Education

B.S. or M.S. in Electrical Engineering

Tools

Cadence

Vivado

Quartus

Lint

CDC

UVM

Git/CI

Job description

Teradyne is seeking an experienced FPGA Engineering Manager to lead a team developing cutting-edge memory test solutions. You will oversee RTL/FPGA design, coordinate with hardware/software/firmware groups, and ensure timely delivery of high-quality products.

The role requires a strong background in Digital ASIC/FPGA design, leadership of 4–6 engineers, and hands-on participation in RTL coding and lab validation. Competitive salary and discretionary bonuses accompany challenging projects.