FPGA Design Engineer for Memory Test Systems

LitePoint; Tualatin (OR); On-site; USD 123,000 - 197,000; Full time

Benefits offered by this job

Medical, dental, vision

Retirement savings plans

Life and disability insurance

Paid vacation & holidays

Tuition assistance

Job summary

Teradyne's Memory Test Division seeks a motivated FPGA Engineer to develop FPGA solutions for next-generation memory test instrumentation. You will work on cutting-edge designs that integrate digital/analog aspects with ASIC/FPGA tech, and collaborate across a global team.

The role requires strong FPGA design skills, RTL, timing closure, and experience with C/C++. Occasional travel is possible, and a base salary is provided with performance-based incentives.

Qualifications

• Bachelor's degree with 5+ years of relevant experience or Master's with 3 years.
• Experience with Digital Design and Architecture.
• RTL coding, synthesis, timing closure and lab validation.
• Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Experience with C or C++.
• Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.

Responsibilities

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers
• Turn abstract concepts and customer requirements into reliable, extensible, and supportable designs.
• Assist in the maintenance and extension of existing FPGA designs to support quality improvement and emerging customer requirements.
• Maintain schedule commitments and deliver high quality end products.
• Occasional travel may be required.

Skills

Digital Design & Architecture

RTL coding, synthesis, timing closure

Static Timing Analysis (ASIC/FPGA)

Digital simulation testbench creation

C/C++

Lab equipment familiarity (oscilloscop

Education

Bachelor's Degree in Electrical Engineering or closely related field

Master's Degree or equivalent in Electrical Engineering or closely related field

Tools

Altera/AMD FPGA tool flows

Verilog HDL

Job description

Teradyne's Memory Test Division seeks a motivated FPGA Engineer to develop FPGA solutions for next-generation memory test instrumentation. You will work on cutting-edge designs that integrate digital/analog aspects with ASIC/FPGA tech, and collaborate across a global team.

The role requires strong FPGA design skills, RTL, timing closure, and experience with C/C++. Occasional travel is possible, and a base salary is provided with performance-based incentives.