FPGA Engineering Manager — Memory Test Solutions

LitePoint; San Jose (CA); On-site; USD 171,000 - 274,000; Full time

Benefits offered by this job

Discretionary bonus

Health benefits

Job summary

Teradyne's Memory Test Division seeks an experienced FPGA Engineering Manager in San Jose to lead a team delivering cutting-edge memory test solutions. You will oversee project execution, guide RTL/Verilog design, and drive cross-functional collaboration with hardware, software, and firmware teams.

The role requires 12+ years in Digital ASIC/FPGA with 5+ years as a project lead, strong Cadence and Verilog skills, and excellent communication.

Qualifications

• BS or MS in Electrical Engineering or closely related field.
• 12+ years of relevant Digital ASIC/FPGA design experience.
• 5+ years as FPGA/ASIC project lead driving multi-project development.
• Experience with RTL coding (Verilog preferred).
• Experience using Cadence digital simulation tools.
• Experience with static timing analysis tools.
• Experience with PCIe, DDR3/4/5, AXI, Ethernet, SPI, SERDES.
• Experience with either AMD or Intel/Altera FPGAs and development tools (Vivado/Quartus).
• Experience with Xilinx/Intel toolchains and CI workflows.
• Excellent presentation and communication skills.

Responsibilities

• Plan, prioritize, and manage multiple FPGA development projects with on-time delivery.
• Represent FPGA team on core project teams and reviews.
• Provide support for sustaining issues.
• Collaborate with hardware, software, and firmware teams for seamless integration of FPGA designs.
• Recruit, onboard, and retain top engineering talent for a high-performing team.
• Set goals and conduct regular performance conversations for 4–6 engineers.
• Contribute to FPGA team process improvement initiatives.
• Provide hands-on guidance on architectures, designs, and specifications.
• Participate in RTL coding, synthesis, timing closure, and lab validation.

Skills

RTL coding

Cadence tools

Static timing analysis

UVM

CI / Source control

Presentation skills

Project scheduling

Lab validation

Digital design quality tools

Education

B.S. or M.S. in Electrical Engineering

Tools

Vivado

Quartus

Cadence simulation tools

Job description

Teradyne's Memory Test Division seeks an experienced FPGA Engineering Manager in San Jose to lead a team delivering cutting-edge memory test solutions. You will oversee project execution, guide RTL/Verilog design, and drive cross-functional collaboration with hardware, software, and firmware teams.

The role requires 12+ years in Digital ASIC/FPGA with 5+ years as a project lead, strong Cadence and Verilog skills, and excellent communication.