Senior FPGA Design Engineer - Memory Test & RTL Architect

Teradyne; Tualatin (OR); On-site; USD 170,400 - 272,600; Full time

Benefits offered by this job

Discretionary bonus

Comprehensive benefits package

Job summary

Teradyne’s Memory Test Division seeks an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM test instrumentation, guide junior engineers, and convert complex customer requirements into robust, extensible implementations.

Ideal candidates have 8+ years in FPGA design, strong RTL/Verilog skills, and experience with FPGA tool flows and lab validation. Occasional travel may be required.

Qualifications

• BS/MS in Electrical Engineering or related field.
• 8+ years of relevant work experience in FPGA design.
• Experience in digital design, RTL coding, timing closure and lab validation.

Responsibilities

• Architect and implement FPGA solutions for memory test instrumentation.
• Provide technical guidance to junior engineers.
• Translate customer requirements into reliable designs.
• Maintain and extend existing FPGA designs for quality and new requirements.
• Meet schedule commitments and deliver high‑quality products.
• Occasional travel may be required.

Skills

Digital design

RTL coding

Timing closure

C/C++

Lab validation

Verilog HDL

Familiarity with FPGA tool flows

UVM methodology

Education

B.S. or M.S. in Electrical Engineering or closely related discipline

Tools

Intel/Xilinx FPGA tool flows

Static Timing Analysis tools

Job description

Teradyne’s Memory Test Division seeks an FPGA Engineer to develop next‑generation memory test solutions. You will architect FPGA designs for Flash and DRAM test instrumentation, guide junior engineers, and convert complex customer requirements into robust, extensible implementations.

Ideal candidates have 8+ years in FPGA design, strong RTL/Verilog skills, and experience with FPGA tool flows and lab validation. Occasional travel may be required.