Senior FPGA Design Engineer – Memory Test Systems

LitePoint; San Jose (CA); On-site; USD 135,000 - 217,000; Full time

Benefits offered by this job

Health and wellness benefits

Retirement savings plans

Paid vacation and holidays

Job summary

Teradyne’s Memory Test Division seeks an FPGA Design Engineer to support memory test instrumentation, combining digital/analog design with ASIC/FPGA tech. The role emphasizes delivering reliable products and collaborating in a global team.

Qualifications include a Bachelor’s in Electrical Engineering with 5+ years of experience, strong RTL/VHDL/Verilog skills, and familiarity with lab gear; travel may be required, and a discretionary bonus may apply.

Qualifications

• Bachelor’s Degree or equivalent in Electrical Engineering or related field, 5+ years of relevant work experience, or Master’s Degree with 3+ years.
• Experience with Digital Design and Architecture.
• RTL coding, synthesis, timing closure and lab validation.
• Experience with Static Timing Analysis of ASICs or FPGAs.
• Experience with digital simulation testbench creation.
• Experience with C or C++.
• Familiarity with lab equipment such as oscilloscopes, power supplies and waveform generators.

Responsibilities

• Architect and implement FPGA solutions to support next generation Flash and DRAM test instrumentation.
• Provide technical guidance to junior engineers
• Turn abstract concepts and customer requirements into reliable, extensible designs.
• Maintain and extend existing FPGA designs to support quality improvements and customer needs.
• Maintain schedule commitments and deliver high quality end products.
• Occasional travel may be required.

Skills

Digital design

RTL coding

C/C++

Verilog HDL

Static timing analysis

Lab validation

Education

Bachelor’s degree in Electrical Engineering or related

Master’s degree or equivalent (optional)

Tools

Verilog HDL tools

FPGA tool flows (Altera/AMD)

Digital simulation tools

Job description

Teradyne’s Memory Test Division seeks an FPGA Design Engineer to support memory test instrumentation, combining digital/analog design with ASIC/FPGA tech. The role emphasizes delivering reliable products and collaborating in a global team.

Qualifications include a Bachelor’s in Electrical Engineering with 5+ years of experience, strong RTL/VHDL/Verilog skills, and familiarity with lab gear; travel may be required, and a discretionary bonus may apply.