Senior Emulation Engineer: Scale Pre-Silicon Flows

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking a Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC.

You will set up emulation flows on Palladium, Veloce, and Zebu, collaborating with architects, RTL, verification, software, and systems teams to accelerate pre-silicon validation across HW/SW. The role requires deep experience in emulation, debugging, regression flows, and scripting, with a focus on performance, reliability, and real-time workloads.

Qualifications

• 10+ years in hardware emulation and/or verification of complex digital systems.
• Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu.
• Ability to debug compile and elaboration issues on emulation platforms.
• Proven ability to set up and optimize emulation regression flows for faster turnaround.
• Strong analytical and problem-solving skills.
• Strong grasp of computer, micro-, and SoC architecture and digital design fundamentals.
• Solid understanding of CDC, clocking, and reset behavior in emulation bring-up.
• Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
• Understanding of memory systems, interconnects, caches, DMA engines, processors, or accelerators.
• Experience debugging complex system-level issues across hardware and software.
• Strong scripting and automation skills for build, regression, and CI pipelines.
• Ability to work effectively in a multidisciplinary team.

Responsibilities

• Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.
• Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.
• Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.
• Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

Hardware emulation

Emulation flows

Debug emulation platforms

Regression flow optimization

Analytical problem solving

SoC architecture fundamentals

CDC & clocking understanding

SystemVerilog & UVM

C/C++ & transactors

Memory systems & DMA

Scripting & automation

Team collaboration

Tools

Palladium

Veloce

Zebu

Job description

Velaura AI, Inc. is seeking a Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC.

You will set up emulation flows on Palladium, Veloce, and Zebu, collaborating with architects, RTL, verification, software, and systems teams to accelerate pre-silicon validation across HW/SW. The role requires deep experience in emulation, debugging, regression flows, and scripting, with a focus on performance, reliability, and real-time workloads.