Senior Emulation Engineer

Velaura AI, Inc.; Santa Clara (CA); On-site; USD 200,000 - 300,000; Full time

Job summary

Velaura AI, Inc. is seeking a Senior Emulation Engineer to own and scale the emulation infrastructure for its next-generation Physical AI SoC.

You will set up emulation flows on Palladium, Veloce, and Zebu, collaborating with architects, RTL, verification, software, and systems teams to accelerate pre-silicon validation across HW/SW. The role requires deep experience in emulation, debugging, regression flows, and scripting, with a focus on performance, reliability, and real-time workloads.

Qualifications

• 10+ years in hardware emulation and/or verification of complex digital systems.
• Hands-on experience setting up emulation flows on Palladium, Veloce, or Zebu.
• Ability to debug compile and elaboration issues on emulation platforms.
• Proven ability to set up and optimize emulation regression flows for faster turnaround.
• Strong analytical and problem-solving skills.
• Strong grasp of computer, micro-, and SoC architecture and digital design fundamentals.
• Solid understanding of CDC, clocking, and reset behavior in emulation bring-up.
• Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
• Understanding of memory systems, interconnects, caches, DMA engines, processors, or accelerators.
• Experience debugging complex system-level issues across hardware and software.
• Strong scripting and automation skills for build, regression, and CI pipelines.
• Ability to work effectively in a multidisciplinary team.

Responsibilities

• Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.
• Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.
• Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.
• Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Skills

Hardware emulation

Emulation flows

Debug emulation platforms

Regression flow optimization

Analytical problem solving

SoC architecture fundamentals

CDC & clocking understanding

SystemVerilog & UVM

C/C++ & transactors

Memory systems & DMA

Scripting & automation

Team collaboration

Tools

Palladium

Veloce

Zebu

Job description

Role Overview

We're looking for a Senior Emulation Engineer to bring up, own, and scale the emulation infrastructure for Velaura's next-generation Physical AI SoC. You'll set up and optimize emulation flows on industry-leading platforms and partner with architects, RTL, verification, software, and system teams to accelerate pre-silicon validation—building confidence in the correctness, performance, reliability, and safety of the design, from individual RTL blocks to full HW/SW systems running real-world workloads at emulation speed.

Responsibilities

• Set up, own, and maintain emulation flows for the Velaura SoC on Palladium, Veloce, and/or Zebu.
• Bring up designs on the emulator, resolving compile/elaboration, capacity/partitioning, and design-mapping issues.
• Build and maintain regression flows, optimizing compile time, run time, throughput, and capacity utilization.
• Support HW/SW co-verification and pre-silicon software bring-up—firmware, drivers, runtime, and OS.
• Optimize on-emulator debug (waveform capture, triggers, visibility) and drive fast root-cause analysis across HW/SW.
• Verify performance, latency, bandwidth, QoS, and real-time behavior under representative workloads.
• Partner with architects, RTL, and verification engineers on emulation strategy, transactor requirements, and coverage goals.
• Emulate compute engines, memory subsystems, interconnect fabrics, control processors, DMA engines, and other core SoC infrastructure.
• Build automation, scripting, and CI hooks for compile and regression pipelines.
• Contribute to FPGA prototyping, pre-silicon validation, and post-silicon debug.
• Apply modern tools, including AI-assisted verification and debug, to improve productivity, quality, and coverage.
• Contribute to a culture of technical excellence and continuous improvement.

Required Qualifications

• 10+ years in hardware emulation and/or verification of complex digital systems.
• Hands‑on experience setting up emulation flows on Palladium, Veloce, or Zebu.
• Ability to debug compile and elaboration issues on emulation platforms.
• Proven ability to set up and optimize emulation regression flows for faster turnaround.
• Strong analytical and problem‑solving skills.
• Strong grasp of computer, micro‑, and SoC architecture and digital design fundamentals.
• Solid understanding of CDC, clocking, and reset behavior in emulation bring‑up.
• Experience with SystemVerilog, UVM, C/C++, transactors, and assertions.
• Understanding of memory systems, interconnects, caches, DMA engines, processors, or accelerators.
• Experience debugging complex system‑level issues across hardware and software.
• Strong scripting and automation skills for build, regression, and CI pipelines.
• Ability to work effectively in a multidisciplinary team.

Preferred Qualifications

• Experience with design partitioning, capacity optimization, and multi‑FPGA/multi‑board emulation scaling.
• Experience with FPGA prototyping and pre‑silicon software bring‑up environments.
• Experience with HW/SW co‑verification and system‑level validation.
• Familiarity with low‑power methodologies and their verification/emulation criteria.
• Experience with AI, machine learning, or edge AI hardware.
• Familiarity with robotics, drones, autonomous vehicles, or industrial automation systems.
• Experience verifying or emulating QoS, latency‑sensitive, or real‑time systems.
• Exposure to performance modeling, profiling, and workload characterization.
• Experience with one or more of the following standards: ISO 26262, IEC 61508, IEC 61511, ISO 13849.
• Experience using modern AI tools and workflows to accelerate engineering productivity.

Background in CPUs, GPUs, AI accelerators, networking and communications silicon, storage and data movement architectures, robotics and autonomous systems, automotive and ADAS platforms, aerospace and defense systems, real‑time and safety‑critical computing, or functional safety architectures and methodologies.

$200,000 - $300,000 a year

Compensation & Benefits

At Velaura, we believe exceptional talent deserves exceptional rewards. Compensation for this role includes a base salary and very competitive equity compensation, allowing team members to share in the company’s long‑term success.

• In addition to base salary and equity compensation, Velaura offers a comprehensive benefits package that may include medical, dental, and vision coverage; paid time off; flexible work arrangements; professional development opportunities; and other benefits designed to support the well‑being and growth of our team.

Velaura is committed to pay equity and transparency and regularly benchmarks compensation to ensure we remain competitive in the market.

Why Velaura?

Velaura is building next‑generation compute technology for cloud, edge, and Physical AI. Our solutions will enable robots, autonomous systems, drones, and other intelligent machines to operate efficiently in the physical world.

This is an opportunity to help build foundational technology at a time when the industry is undergoing fundamental change. You will work alongside experienced leaders, architects, engineers, and operators who have delivered industry‑defining products across mobile, cloud, semiconductor, and AI platforms. If you enjoy solving difficult problems, working across disciplines, and helping shape the future of Physical AI, we would love to hear from you.

Equal Employment Opportunity and Accommodations

Velaura is an Equal Opportunity Employer that is committed to inclusion and diversity. Qualified applicants will receive consideration for employment without regard to race, color, religion, national origin, gender, sexual orientation, gender identity, disability or protected veteran status. We also take affirmative action to offer employment opportunities to minorities, women, individuals with disabilities, and protected veterans.

Velaura is committed to working with qualified individuals with physical or mental disabilities. Applicants who would like to contact us regarding the accessibility of our website or who need special assistance or a reasonable accommodation for any part of the application or hiring process may contact us at: [email protected]. This contact information is for accommodation requests only. Evaluation of requests for reasonable accommodation will be determined on a case‑by‑case basis.

We may use artificial intelligence (AI) tools to support parts of the hiring process, such as reviewing applications, analyzing resumes, or assessing responses and identifying potential inconsistencies or verification signals in application materials based on available information. These tools assist our recruitment team but do not replace human judgment. Final hiring decisions are ultimately made by humans. If you would like more information about how your data is processed, please contact us.