Senior Electromagnetics R&D Engineer — High-Speed SERDES

Synopsys Inc; Boxborough (MA); On-site; USD 150,000 - 190,000; Full time

Job summary

Synopsys Inc. seeks an experienced R&D Engineer specializing in electromagnetics and high-speed SERDES extraction tools. You will shape flows for 3DIC designs and 10–500Gbps products, leveraging Helic, HFSS, and ADS to ensure EM integrity across CMOS, FinFET, and GAA technologies.

You will collaborate with a globally distributed design team, lead methodology efforts, and drive solutions from concept to deployment, advancing Synopsys' leadership in chip design and verification.

Qualifications

• 10+ years of experience in CMOS, FinFET, and GAA technologies.
• Proficiency with Helic, HFSS and ADS tools.
• Strong understanding of electromagnetic theory in high-speed design.
• Ability to develop and implement electromagnetic extraction and simulation methodologies.
• Experience with RF spice simulations and proper tool settings.

Responsibilities

• Define and develop EM extraction and simulation flows for the state of the art 3DIC designs and SERDES products operating from 10Gbps to 500Gbps.
• Collaborate with cross-functional teams to address and resolve electromagnetic issues.
• Provide technical expertise in the use of Helic, HFSS, and ADS tools.
• Lead and contribute to the design and methodology team to enhance product performance.
• Ensure effective deployment of solutions in collaboration with other domain experts.
• Analyze challenges fundamentally and define pragmatic and practical solutions.

Skills

CMOS FinFET GAA

Electromagnetic theory

EM extraction methodologies

RF spice simulations

Tools

Helic

HFSS

ADS

Job description

Synopsys Inc. seeks an experienced R&D Engineer specializing in electromagnetics and high-speed SERDES extraction tools. You will shape flows for 3DIC designs and 10–500Gbps products, leveraging Helic, HFSS, and ADS to ensure EM integrity across CMOS, FinFET, and GAA technologies.

You will collaborate with a globally distributed design team, lead methodology efforts, and drive solutions from concept to deployment, advancing Synopsys' leadership in chip design and verification.