Principal SoC IP & Interconnect Architect: Lead Next-Gen

Ampere; Portland (OR); Sur place; USD 182 000 - 273 000; Plein temps

Avantages offerts par ce poste

Health insurance

401K retirement plan

Unlimited flextime

Paid holidays

Résumé du poste

Ampere is seeking a Principal SoC IP & Interconnect Architect to define and integrate advanced IP for next-generation Ampere products. You will drive high-performance I/O and interconnect subsystem architecture and collaborate with system architects, design, verification, and software teams to deliver cohesive IP solutions.

Candidate should have 6+ years in SoC architecture, AMBA AXI/CHI knowledge, cache-coherent memory systems, and end-to-end IP lifecycle experience, with strong performance

Qualifications

• 6+ years of proven SoC architecture or design experience.
• Familiar with SoC interconnect and coherent fabric architecture.
• Deep understanding of AMBA-based interconnect protocols (AXI and CHI).
• Knowledge of cache-coherent memory systems, DMA traffic, interconnect tradeoffs.
• Hands-on experience developing architectural performance models for bandwidth, latency, scalability, workloads.
• Experience across the full IP lifecycle, from IP selection and integration through silicon validation and bring-up.
• Additional skills: RTL/Logic Design or Design Verification, IP Integration: Boot/Reset Flows, Power Delivery, Clocking, Debug/Trace, Interrupts, RAS

Responsabilités

• Lead the definition, architecture, and integration of SoC and interconnect IP for next-gen Ampere products.
• Own the end-to-end architecture of one or more I/O and interconnect subsystems, balancing performance, scalability, power, reliability, and platform requirements.
• Drive cross-functional alignment with system architects, design, verification, and software teams to deliver cohesive, production-ready SoC IP solutions.
• Outline subsystem interfaces, integration strategies, and architectural requirements for seamless connectivity across the SoC platform.
• Define subsystem-level SoC architecture in collaboration with CPU and compute-engine teams, aligning with the SoC chassis, global architecture, and integration requirements.
• Influence key technical decisions and resolve complex architecture and integration tradeoffs throughout the product development lifecycle.

Connaissances

SoC architecture

Interconnect architecture

AMBA AXI/CHI

Cache-coherent memory systems

Performance modeling

RTL/Logic Design

Design Verification

IP integration

Formation

BS in Electrical Engineering, Computer Engineering, or Computer Science; 8+ years

Description du poste

Ampere is seeking a Principal SoC IP & Interconnect Architect to define and integrate advanced IP for next-generation Ampere products. You will drive high-performance I/O and interconnect subsystem architecture and collaborate with system architects, design, verification, and software teams to deliver cohesive IP solutions.

Candidate should have 6+ years in SoC architecture, AMBA AXI/CHI knowledge, cache-coherent memory systems, and end-to-end IP lifecycle experience, with strong performance