Senior Analog IC Architect — SerDes & High-Speed I/O

Cadence

Mount Royal (NJ)

On-site

USD 180,000 - 240,000

Full time

14 days+
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Job summary

Cadence is seeking a Design Architect Analog IC Designer with 10+ years of CMOS SerDes experience to lead design and verification from concept through customer conformance. The role emphasizes high-speed I/O, jitter control, and advanced CAD tool use in ≤16nm processes.

Ideal candidates have strong problem-solving and communication skills, with proficiency in Cadence and lab testing. Collaboration across teams is essential to deliver complex SerDes blocks at ≥16Gbps.

Qualifications

  • Minimum 10 years of experience in CMOS SerDes or high-speed I/O IC development.
  • Thorough understanding of jitter and signal equalization techniques.
  • Proficient in SerDes blocks: Driver, Receiver, Serializer, Deserializer, Phase Interpolator, PLL, clock distribution, ADC/DAC, Bandgap, regulators.
  • Excellent problem-solving and communication skills; able to work in a team.
  • Experience with Cadence tools, lab testing, and post-layout verification is a plus.

Responsibilities

  • Design and develop analog/mixed-signal IC blocks from concept to verification.
  • Contribute to long-reach SerDes architecture and implementation.
  • Use CAD tools to simulate circuits and verify layouts post-layout.
  • Collaborate with cross-functional teams to meet customer specifications.

Skills

Problem-solving
Communication
Teamwork

Education

MS/PhD in EE

Tools

CAD tools
Cadence
Lab tests
Layout entry
Post-layout verification
16Gbps design
≤16nm tech

Job description

Cadence is seeking a Design Architect Analog IC Designer with 10+ years of CMOS SerDes experience to lead design and verification from concept through customer conformance. The role emphasizes high-speed I/O, jitter control, and advanced CAD tool use in ≤16nm processes.

Ideal candidates have strong problem-solving and communication skills, with proficiency in Cadence and lab testing. Collaboration across teams is essential to deliver complex SerDes blocks at ≥16Gbps.

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