Lead Analog IC Design Engineer – High-Speed SerDes

Cadence

San Jose (CA)

On-site

USD 119,000 - 221,000

Full time

14 hours ago
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Benefits offered by this job

401(k) plan with employer match
Medical, dental and vision plans
Paid vacation and holidays

Job summary

Cadence seeks a Lead Analog IC Design Engineer in California to drive analog and mixed-signal circuits from concept to final verification, ensuring compliance with customer requirements and industry standards. You will lead CMOS SerDes and high-speed I/O blocks, mentor engineers, and collaborate with cross-functional teams to deliver robust, high-performance designs for cutting-edge applications.

Strong communication, problem-solving, and knowledge of jitter/clocking are essential.

Qualifications

  • 3+ years designing CMOS SerDes or high-speed I/O ICs.
  • Experience with SerDes blocks: TX/RX, serializers/deserializers, PLLs, clock distribution, bias circuits.
  • Understanding of jitter and signal-equalization techniques.
  • Proficiency with CAD tools for circuit simulation, layout, and verification.
  • Master’s or Ph.D. in Electrical Engineering.
  • Strong problem-solving and communication; team player.

Responsibilities

  • Lead analog IC design from concept through verification to meet customer specs.
  • Collaborate with cross-functional teams to ensure design success.
  • Mentor junior engineers and contribute to design reviews.

Skills

CMOS SerDes design
analog/mixed-signal design
CAD tools for circuit simulation
team collaboration
communication skills
high-speed I/O knowledge

Education

Master’s degree or Ph.D. in electrical engineering

Tools

Cadence design tools
circuit simulation tools
layout verification tools

Job description

Cadence seeks a Lead Analog IC Design Engineer in California to drive analog and mixed-signal circuits from concept to final verification, ensuring compliance with customer requirements and industry standards. You will lead CMOS SerDes and high-speed I/O blocks, mentor engineers, and collaborate with cross-functional teams to deliver robust, high-performance designs for cutting-edge applications.

Strong communication, problem-solving, and knowledge of jitter/clocking are essential.

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