Senior Director of Engineering (High-Speed SERDES)

SBT; San Francisco (CA); On-site; USD 160,000 - 230,000; Full time

Job summary

A confidential startup company in San Francisco is looking for a Senior Silicon Development Engineer to lead advanced-node semiconductor programs. The ideal candidate will have over 10 years of experience in semiconductor engineering and be skilled in high-speed interface design and chip tape-out processes. This role requires strong technical leadership and the ability to manage relationships with external partners. Join this innovative team aiming to solve significant challenges in computing systems.

Qualifications

• 10+ years of experience in semiconductor engineering with increasing responsibility.
• 3+ years of senior-level management experience.
• Proven expertise in leading chip tape-out processes.

Responsibilities

• Lead advanced-node semiconductor programs from architectural definition through production readiness.
• Provide technical leadership for high-speed electrical and electro-optical interfaces.
• Define and oversee design and verification workflows across domains.
• Manage relationships with foundries and engineering partners.

Skills

Semiconductor engineering

Technical leadership

Design organization development

Chip tape-out processes

Education

Advanced technical engineering degree (MSEE, PhD)

Job description

SBT is the exclusive executive recruiting firm for this confidential position.

Company Overview

This confidential, well-funded startup company is developing next-generation solutions aimed at solving bandwidth and connectivity challenges in advanced computing systems. Their core technology enables high-speed, scalable data movement to support emerging infrastructure demands that power AI workloads.

Role Responsibilities

• Silicon Development Ownership: Lead and deliver complex, advanced-node semiconductor programs from architectural definition through tape-out and production readiness, ensuring technical rigor, schedule alignment, and execution quality across all design phases.
• High-Speed Interface & Photonic Co-Design: Provide technical leadership for high-speed electrical and electro-optical interfaces, including SerDes, optical driver, and receiver architectures. Partner closely with photonics teams to establish robust co-design practices spanning electrical, optical, and packaging domains.
• Design Execution & Silicon Validation: Define and oversee end-to-end design and verification workflows across digital, analog, and physical domains, from early implementation through signoff and silicon handoff. Lead post-silicon bring-up, characterization, and debug of high-speed interfaces, ensuring performance targets are met and enabling reliable system integration and production readiness.
• External Partnerships & Execution Governance: Manage relationships with foundries, OSATs, IP vendors, and external engineering partners, setting clear milestones and accountability to support cost control, risk mitigation, and on-time delivery.

Qualifications

• 10+ years of experience in semiconductor engineering, with a history of increasing technical and organizational responsibility across advanced-node silicon development programs.
• 3+ years of experience in senior-level management, building out a design organization from scratch
• Advanced technical engineering degree (MSEE, PhD)
• Proven expertise with leading end-to-end chip tape-out processes