Senior Analog IC Designer, High-Speed SerDes + Equity

Cadence Design Systems; San Jose (CA); Hybrid; USD 137,000 - 254,000; Full time

Benefits offered by this job

Bonus

Equity

Benefits

Job summary

Cadence Design Systems in SAN JOSE seeks a Principal Analog IC Design Engineer focused on high-speed SerDes. You will lead the design and development of analog/mixed-signal blocks from concept to verification in advanced CMOS processes, collaborating with cross-functional teams to meet customer specifications.

Requirements include 7+ years in CMOS SerDes or high-speed I/O, deep knowledge of jitter and equalization, and hands-on CAD tool proficiency.

Qualifications

• 7+ years of CMOS SerDes or high-speed I/O IC design experience.
• Working knowledge of SerDes standards and electrical requirements.
• Thorough understanding of jitter and signal equalization techniques.
• Proficient with CAD tools for circuit simulation, layout and verification.
• Experience with Cadence tool suite and lab testing a plus.

Responsibilities

• Design and develop analog/mixed-signal IC blocks from concept/specification through verification.
• Lead block-level design including Driver, Receiver, Serializer/Deserializer, PLL, clock distribution, and regulators.
• Collaborate with cross-functional teams to meet customer specifications.

Job description

Cadence Design Systems in SAN JOSE seeks a Principal Analog IC Design Engineer focused on high-speed SerDes. You will lead the design and development of analog/mixed-signal blocks from concept to verification in advanced CMOS processes, collaborating with cross-functional teams to meet customer specifications.

Requirements include 7+ years in CMOS SerDes or high-speed I/O, deep knowledge of jitter and equalization, and hands-on CAD tool proficiency.