Senior Digital Design Lead – PCIe/SoC Frontend

Astera Labs; San Jose (CA); On-site; USD 140,000 - 190,000; Full time

Benefits offered by this job

Flexible time off in the US

Parental leave

401K

Retirement and pension plans

Competitive medical, dental and vision

Job summary

Astera Labs seeks a Senior Digital Design Engineer in the United States to develop micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high-performance network controllers.

The role requires strong knowledge of PCI-Express, Ethernet, and related protocols, with hands-on experience in verification, bring-up, and debug across complex SoC blocks.

Qualifications

• Bachelor’s degree in EE required; Master’s preferred.
• Strong background in electrical engineering and front-end SoC design.
• Experience with PCIe, Uplink, Esun, Ethernet protocols.

Responsibilities

• Develop micro-architecture and front-end circuit design (RTL, synthesis, timing).
• Lead block-level verification from architecture to GDS.
• Support or develop complex SoC/silicon products for networking/server applications.

Skills

RTL design

Synthesis

IP integration

Front-end verification

High-speed protocols

Python scripting

Education

Bachelor's in EE

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Verilog/VHDL

Job description

Astera Labs seeks a Senior Digital Design Engineer in the United States to develop micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high-performance network controllers.

The role requires strong knowledge of PCI-Express, Ethernet, and related protocols, with hands-on experience in verification, bring-up, and debug across complex SoC blocks.