Senior Digital Design Engineer: High-Perf Network ASIC

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 150,000 - 230,000; Full time

Job summary

Astera Labs is seeking a Senior Digital Design Engineer in San Jose to drive front-end circuit design, RTL, and verification for high-performance network controllers. You will own architecture, RTL, synthesis, IP integration, and block-level verification across PCIe, UALink, Esun, and Ethernet interfaces.

The role demands a strong SoC/silicon background, 3+ years of related experience, and the ability to work independently in a fast-paced US environment.

Qualifications

• Bachelor in Electrical Engineering is required; Master preferred.
• +3 years’ experience in SoC/silicon products for Switch ASIC, Networking, or Server/Storage.
• Ability to prioritize multiple tasks and work with minimal supervision.
• Entrepreneurial, open-minded attitude; customer-focused execution.
• Authorized to work in the US and available to start immediately.

Responsibilities

• Develop micro-architecture and front-end circuit design, including RTL, synthesis, IP integration, and block-level verification.
• Work with PCIe Gen-3 and above, Ualink, Esun, Ethernet interfaces.
• End-to-end ownership from architecture to GDS.
• Collaborate with design teams using Synopsys and Cadence tool flows.

Skills

Front end design

Timing closure

DFT

Block-level ownership

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Synopsys

Cadence

UVM

DFT

Job description

Astera Labs is seeking a Senior Digital Design Engineer in San Jose to drive front-end circuit design, RTL, and verification for high-performance network controllers. You will own architecture, RTL, synthesis, IP integration, and block-level verification across PCIe, UALink, Esun, and Ethernet interfaces.

The role demands a strong SoC/silicon background, 3+ years of related experience, and the ability to work independently in a fast-paced US environment.