Senior Digital Design Lead – PCIe/CXL ASICs

Astera Labs; San Jose (CA); On-site; USD 216,000 - 240,000; Full time

Benefits offered by this job

Discretionary bonus

Job summary

Astera Labs in San Jose, CA, is seeking a Senior Manager/Manager, Digital Design, to lead front-end digital design for high‑performance PCIe & CXL devices, guiding RTL development, verification, physical design, tape-out, and product shipment.

This role offers the chance to influence the development of purpose-built connectivity products for AI infrastructure and to establish scalable design practices while delivering silicon that advances next-generation AI systems.

Qualifications

• Bachelor’s degree in Electrical Engineering, Computer Engineering, or a related technical field.
• Experience with PCIe & CXL, UAL, Ethernet digital design, including protocol implementation.
• 3-5 years of engineering management or technical leadership in digital IC or ASIC design.
• Demonstrated ownership of chip design and development from requirements through tape-out and shipment for at least two devices of reasonable complexity.
• Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tape-out quality.
• Ability to lead 6–8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Responsibilities

• End-to-End Chip Development: lead RTL through production shipment.
• Deliver at least two complex devices with milestones and risk tracking.
• Translate PCIe/CXL, UAL, Ethernet requirements into robust digital implementations.
• Establish design checklists, review gates, and signoff criteria.
• Collaborate with verification, physical design, DFT, and validation teams to resolve issues.
• Communicate status and mitigation plans to leadership.

Skills

Front-end RTL

Engineering management

Digital IC design

PCIe/CXL protocols

Team leadership

Education

BSc in Electrical/Computer Engineering

Masters/PhD preferred

Job description

Astera Labs in San Jose, CA, is seeking a Senior Manager/Manager, Digital Design, to lead front-end digital design for high‑performance PCIe & CXL devices, guiding RTL development, verification, physical design, tape-out, and product shipment.

This role offers the chance to influence the development of purpose-built connectivity products for AI infrastructure and to establish scalable design practices while delivering silicon that advances next-generation AI systems.