Principal Digital Design Architect for AI Connectivity SoCs

Asteralabs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs seeks a Principal Digital Design Engineer to architect and implement next-gen digital designs for AI connectivity. You will own blocks from micro-architecture to silicon bring-up, driving RTL and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5.

This role offers work on cutting-edge AI infrastructure with ownership of critical design challenges in a fast-paced,

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis.
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation.
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar.

Responsibilities

• Design ownership and execution for complex digital blocks and subsystems, aiming for optimal power, performance and area in <7nm technologies.
• Lead timing closure and implement DFT features for production-ready designs.
• Drive designs to production with accountability for quality, schedule, and success.
• Collaborate with verification teams to develop test plans and achieve coverage closure.
• Mentor junior engineers and contribute to CAD/automation improvements.

Skills

RTL coding

Timing closure

DFT implementation

SoC architecture

CAD automation

Education

Bachelor's degree in Electrical Engineering or equivalent

Master's degree in Electrical Engineering or related field

Tools

Cadence digital design flows

Synopsys digital design flows

Job description

Astera Labs seeks a Principal Digital Design Engineer to architect and implement next-gen digital designs for AI connectivity. You will own blocks from micro-architecture to silicon bring-up, driving RTL and collaborating with verification, physical design, and DFT teams to deliver production-quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5.

This role offers work on cutting-edge AI infrastructure with ownership of critical design challenges in a fast-paced,