Senior Digital Design Engineer — PCIe & Ethernet

Astera Labs; San Jose (CA); On-site; USD 120,000 - 190,000; Full time

Benefits offered by this job

Health benefits

Job summary

Astera Labs in San Jose, CA is seeking Digital Design Engineers to contribute to front-end circuit design, RTL, and IP integration for high performance network controllers. You will work on front-end architecture, RTL coding, and integration with signaling protocols to meet stringent latency and bandwidth requirements.

Applicants should have a strong EE background with hands-on experience in PCIe, Ualink, Esun and Ethernet, plus verification, DFT, and silicon bring-up capabilities.

Qualifications

• Hands-on front-end design with RTL, simulations, and synthesis experience.
• Experience with high-speed protocols such as PCIe, Ualink, Esun, Ethernet.
• Familiarity with UVM-based design verification and DFT concepts.
• Silicon bring-up and debug experience.
• Proactive, self-motivated with strong technical communication.

Skills

Front-end design

RTL

Synthesis

IP integration

High-speed protocols

Debugging

Education

Bachelor's degree in Electrical Engineering

Master's degree in Electrical Engineering

Tools

Synopsys

Cadence

Job description

Astera Labs in San Jose, CA is seeking Digital Design Engineers to contribute to front-end circuit design, RTL, and IP integration for high performance network controllers. You will work on front-end architecture, RTL coding, and integration with signaling protocols to meet stringent latency and bandwidth requirements.

Applicants should have a strong EE background with hands-on experience in PCIe, Ualink, Esun and Ethernet, plus verification, DFT, and silicon bring-up capabilities.