Senior Digital Design Engineer – High-Speed Network FrontEnd

Astera Labs; San Jose, Northern (CA, KY); Hybrid; USD 110,000 - 180,000; Full time

Benefits offered by this job

Restaurant d'entreprise

Job summary

Astera Labs in the United States is seeking Digital Design Engineers with experience developing micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high‑performance network controllers.

The candidate should know PCIe Gen-3 and above, Ualink, Esun, Ethernet, and be hands-on with Synopsys/Cadence flows, DFT, and UVM verification; Bachelor’s in EE required, Master’s preferred, and US work authorization.

Qualifications

• Bachelor's degree in electrical engineering is required; master's preferred.
• Experience with high-speed protocols and ASIC front-end design.
• Experience with RTL, simulations, and synthesis.
• Familiarity with DFT and UVM-based verification is advantageous.

Responsibilities

• Develop front-end circuit architecture and RTL implementations.
• Integrate IP and perform synthesis for high-performance network controllers.
• Work with Synopsys/Cadence design flows and debug silicon bring-up.

Skills

Front-end design

RTL

Synthesis

UVM verification

Education

Bachelor's degree in Electrical Engineering

Master's degree preferred

Tools

Synopsys tools

Cadence tools

Python scripting

Job description

Astera Labs in the United States is seeking Digital Design Engineers with experience developing micro-architecture and front-end circuit design, including RTL, synthesis, and IP integration for high‑performance network controllers.

The candidate should know PCIe Gen-3 and above, Ualink, Esun, Ethernet, and be hands-on with Synopsys/Cadence flows, DFT, and UVM verification; Bachelor’s in EE required, Master’s preferred, and US work authorization.