Digital Design Manager – PCIe/CXL Front-End Lead

Astera Labs; San Jose (CA); On-site; USD 216,000 - 240,000; Full time

Job summary

Astera Labs in San Jose, CA seeks a Senior Manager/Manager, Digital Design to lead front-end digital design for high-performance PCIe and CXL devices that enable reliable rack-scale AI infrastructure. You will guide projects from requirements through RTL development, verification, physical design, tap-out, and shipment, ensuring performance, quality, and on-time delivery.

This role offers the opportunity to build scalable design practices at a hyper-growth company and to deliver silicon that

Qualifications

• Bachelor’s degree in Electrical/Computer Engineering or a related technical field.
• Experience with PCIe & CXL, UAL, ethernet digital design, including protocol implementation, high-speed connectivity requirements, and physical-layer considerations.
• 3-5 years of experience in engineering management or technical leadership in digital IC or ASIC design.
• Demonstrated ownership of chip design and development from requirements through tap-out and shipment for at least two devices of reasonable complexity.
• Strong hands-on expertise developing front-end RTL and applying design practices that support predictable physical design progress and tap-out quality.
• Ability to lead 6-8 engineers and influence execution across architecture, verification, physical design, DFT, firmware, validation, and operations.

Responsibilities

• Lead digital design execution from product requirements and architecture through RTL, verification, tap-out, and production shipment.
• Drive delivery of at least two complex devices, maintaining clear milestones, technical decisions, risk tracking, and schedule accountability.
• Partner with architecture and system teams to translate PCIe & CXL, UAL, ethernet requirements into robust, scalable digital implementations.
• Set expectations for high-quality front-end RTL that enables efficient synthesis, timing closure, physical implementation, and smooth tap-out.
• Establish and maintain design checklists, review gates, coding standards, and signoff criteria across the digital design lifecycle.
• Resolve design, performance, power, area, clocking, and integration issues in partnership with verification, physical design, DFT, and validation teams.
• Lead, mentor, and develop a team of 6-8 digital design engineers, fostering technical excellence, accountability, and effective collaboration.
• Influence cross-functional development decisions and align engineering teams around quality, risk reduction, and on-time execution.
• Communicate technical status, tradeoffs, dependencies, and mitigation plans to engineering and program leadership.

Skills

Digital design leadership

RTL development

Front-end RTL

Team leadership

High-speed interfaces

Education

Bachelor’s degree in Electrical/Computer Engineering

Master’s or PhD in Electrical/Computer Engineering

Job description

Astera Labs in San Jose, CA seeks a Senior Manager/Manager, Digital Design to lead front-end digital design for high-performance PCIe and CXL devices that enable reliable rack-scale AI infrastructure. You will guide projects from requirements through RTL development, verification, physical design, tap-out, and shipment, ensuring performance, quality, and on-time delivery.

This role offers the opportunity to build scalable design practices at a hyper-growth company and to deliver silicon that