Principal Digital Design Engineer – AI Connectivity & SoC

Astera Labs; San Jose (CA); On-site; USD 185,000 - 230,000; Full time

Job summary

Astera Labs seeks a Principal Digital Design Engineer to architect and implement next‑generation digital designs for high‑performance AI connectivity solutions.

You will own blocks from micro‑architecture through silicon bring‑up, driving RTL and coordinating with verification, physical design, and DFT teams to deliver production‑quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.

Qualifications

• Bachelor's degree in Electrical Engineering or equivalent.
• 10+ years of hands-on experience developing complex SoC/silicon products in Server, Storage, and/or Networking markets.
• Expertise in architecture definition, micro-architecture development, RTL coding, functional simulation, and synthesis.
• Strong understanding of timing closure, gate-level simulation (GLS), and DFT implementation.
• Deep expertise in at least one high-speed protocol: PCIe, CXL, Ethernet, DDR, or similar.
• Production experience with advanced CMOS nodes (≤7nm).
• Proficiency with Cadence and/or Synopsys digital design flows.

Responsibilities

• Design ownership and implement complex digital blocks and subsystems from micro-architecture to RTL.
• Drive timing closure and implement DFT features for performance.
• Lead production-ready designs with quality and schedule accountability.
• Collaborate with verification teams to develop test plans and achieve coverage.
• Own third-party IP integration and block-level verification through sign-off.
• Mentor junior engineers and drive CAD automation improvements.

Skills

RTL coding

Timing closure

DFT implementation

Synthesis

Cadence flows

Verification collaboration

IP integration

Mentoring

Hardware debugging

Education

Bachelor's degree in Electrical Engineering

Tools

Cadence tools

Synopsys tools

Job description

Astera Labs seeks a Principal Digital Design Engineer to architect and implement next‑generation digital designs for high‑performance AI connectivity solutions.

You will own blocks from micro‑architecture through silicon bring‑up, driving RTL and coordinating with verification, physical design, and DFT teams to deliver production‑quality silicon supporting PCIe Gen 6/7, CXL, UALink, UCI, Ethernet, and DDR4/DDR5 protocols.