ASIC Engineer, Design Verification

Anysilicon; Sunnyvale (CA); Hybrid; USD 120,000 - 180,000; Full time

Job summary

Meta in Sunnyvale, CA is seeking an ASIC Design Verification Engineer to join its Infrastructure organization, focusing on developing advanced ASIC solutions for data center applications.

You will build verification test benches, define verification plans, and drive closure using UVM, Formal and Emulation, collaborating with design teams to ensure high-quality silicon.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience.
• 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification.
• 2+ years of verification of block/IP/SoC using SystemVerilog UVM/OVM methodologies.
• Experience with Python, TCL, Perl, Shell for building verification environments.

Responsibilities

• Define and implement verification plans for block/IP/SoC designs.
• Build verification test benches for block/IP/sub-system/SoC level verification.
• Develop functional tests based on verification plans.
• Drive DV closure using defined metrics including coverage.
• Debug and resolve functional failures with the Design team.
• Collaborate with cross-functional teams to ensure design quality through verification metrics.

Skills

SystemVerilog/UVM

C/C++ verification

Test bench development

Code coverage

Debug skills

UVM from scratch

Education

Bachelor's degree in CS/CE

Tools

Python

TCL

Perl

Shell scripting

Git

Job description

Meta, 1180 Discovery Way, Sunnyvale, CA 94089

Job Description:

Meta is seeking an ASIC Design Verification Engineer to join its Infrastructure organization, focusing on developing advanced ASIC solutions for data center applications. The role involves collaborating with experienced engineers to ensure the verification closure of design modules or sub-systems, utilizing various methodologies including UVM, Formal, and Emulation to achieve high-quality designs.

Responsibilities:

• Define and implement verification plans for block/IP/System on Chip (SoC) designs.
• Build verification test benches for block/IP/sub-system/SoC level verification.
• Develop functional tests based on verification test plans.
• Drive Design Verification to closure based on defined metrics, including functional and code coverage.
• Debug and resolve functional failures in collaboration with the Design team.
• Work with cross-functional teams to ensure design quality through established verification metrics.

Qualifications:

• Bachelor's degree in Computer Science, Computer Engineering, or a relevant technical field, or equivalent practical experience (must be completed prior to joining).
• 2+ years of hands-on experience in SystemVerilog/UVM methodology or C/C++ based verification.
• 2+ years of experience in block/IP/sub-system and/or SoC level verification using SystemVerilog UVM/OVM methodologies.
• Experience with EDA tools and scripting languages (Python, TCL, Perl, Shell) for building verification environments.

Skills:

• Experience with Application-Specific Integrated Circuit (ASIC) development cycles leading to first-pass success.
• Familiarity with revision control systems like Mercurial, Git, or SVN.
• Ability to develop UVM-based verification environments from scratch.
• Knowledge of high-speed interface verification (e.g., PCIe, DDR, Ethernet).
• Experience in architecting Design Verification infrastructure and executing full verification cycles.
• Verification experience with ARM/RISC-V based sub-systems or SoCs.
• Familiarity with data-center applications involving Video, AI/ML, and Networking designs.