Senior ASIC Frontend Implementation Engineer (SoC/CDC)

Meta; Sunnyvale (CA); On-site; USD 146,000 - 209,000; Full time

Benefits offered by this job

Equity

Bonus

Benefits

Job summary

Meta is hiring ASIC Frontend Implementation Engineers in Sunnyvale, CA. The role focuses on RTL-to-netlist implementation for data center SoCs and IP, including Lint, CDC analysis, timing constraints, and synthesis.

You’ll work with Design, DV, Emulation, and Physical Design teams to optimize timing, area, and power. Qualified candidates have a strong background in SystemVerilog HDL, front-end flows, and experience with Design Compiler, Spyglass, or PrimeTime.

Qualifications

• Bachelor's degree in Computer Science, Computer Engineering or equivalent practical experience.
• 6+ years of experience in static verification tools including RTL Lint and CDC analysis.
• Experience with SOC CDC signoff and front-end ASIC flows.

Responsibilities

• Perform clock domain crossing analyses and sign-off for CDC several designs.
• Perform reset domain crossing checks and collaborate with design and FW teams.
• Perform RTL lint and work with designers to create waivers.
• Perform RTL DFT analysis and improve scan coverage for stuck-at faults.
• Run logic/physical synthesis to generate optimized gate-level netlists.
• Develop automation scripts and methodologies for FE-tools (Lint, CDC, RDC).
• Collaborate with design, DV, emulation, and physical design teams for handoff and timing feedback.

Skills

Static verification tools

RTL Lint

CDC analysis

Scripting (Perl/Python/TCL)

Education

Bachelor's degree in CS/CE or equivalent

Tools

Design Compiler

Spyglass

PrimeTime

Make

Job description

Meta is hiring ASIC Frontend Implementation Engineers in Sunnyvale, CA. The role focuses on RTL-to-netlist implementation for data center SoCs and IP, including Lint, CDC analysis, timing constraints, and synthesis.

You’ll work with Design, DV, Emulation, and Physical Design teams to optimize timing, area, and power. Qualified candidates have a strong background in SystemVerilog HDL, front-end flows, and experience with Design Compiler, Spyglass, or PrimeTime.