Senior Digital ASIC Architect - High-Speed Silicon

020 Cisco Systems, Inc.

Carlsbad (CA)

On-site

USD 166,000 - 238,000

Full time

43 hours ago
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Job summary

Cisco Systems, Inc. Silicon One team is hiring a Digital Design Technical Leader to own the full ASIC lifecycle—from RTL to tapeout and post-silicon bring-up.

You will guide digital, analog, firmware, and physical design teams, setting architectures and integrating high‑speed IPs to deliver 100G/200G/400G silicon for AI-era networks. You will push power and timing budgets while ensuring verification, IP integration, and automation support across the full flow.

Qualifications

  • Bachelor’s degree with 8+ years in digital design and ASIC/SoC work.
  • Experience leading full ASIC/SoC design flow from RTL to GDSII.
  • Hands-on with SerDes, Ethernet and high-speed IP integration.
  • Strong cross-functional leadership and design-for-test familiarity.

Responsibilities

  • Lead digital architecture for high-speed datapaths and control planes.
  • Own RTL-to-GDSII flow, post-silicon bring-up and validation.
  • Define specifications balancing power, timing, and hardware/firmware trade-offs.
  • Integrate SerDes and DSP IPs and verify complex blocks.
  • Develop backend scripts for QoR metrics and timing closure.
  • Collaborate with cross-functional teams to resolve design issues.

Skills

Digital design
FSMs
CPU subsystems
SoCs
FPGA validation
Verifications
Power/Timing budgeting

Education

Bachelor's degree in electrical engineering or related field
Master's degree in electrical engineering or related field
PhD in electrical engineering or related field

Tools

SerDes IP integration
DSP IPs integration
GDSII signoff
ASIC/SoC design flow

Job description

Cisco Systems, Inc. Silicon One team is hiring a Digital Design Technical Leader to own the full ASIC lifecycle—from RTL to tapeout and post-silicon bring-up.

You will guide digital, analog, firmware, and physical design teams, setting architectures and integrating high‑speed IPs to deliver 100G/200G/400G silicon for AI-era networks. You will push power and timing budgets while ensuring verification, IP integration, and automation support across the full flow.

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