Senior ASIC Design Lead

Cisco Systems, Inc.; San Jose (CA); On-site; USD 187,000 - 268,000; Full time

Benefits offered by this job

401(k) with company match

Medical, dental & vision insurance

Paid parental leave

Stock grants & RSUs

Job summary

Silicon One is Cisco's leading hardware team responsible for cutting-edge AI-era silicon powering core Switching, Routing, and Wireless products. This role focuses on high-quality structural/functional test, diagnostic features, IP development, and robust test access within Cisco’s scalable silicon architecture.

Join a global, collaborative team that drives performance, security, and innovation across Cisco’s silicon platforms, working closely with RTL and backend design groups to deliver

Qualifications

• 10+ years of experience in ASIC digital design.
• Proficiency in Verilog/SystemVerilog coding.
• Experience with CDC/RDC concepts and design implementation.
• Proficiency with front-end tools (Verilog simulators, linting, CDC checkers, synthesis, formal verification).

Responsibilities

• You will drive high-quality Structural test, functional test and diagnostic feature implementation.
• IP development and integration, and test access including high speed IO with protocol.
• Collaborate with Front-end RTL and backend physical design teams to understand chip architecture.

Skills

ASIC design

Verilog/SystemVerilog

CDC/RDC concepts

EDA front-end tools

AMBA interfaces

Education

Bachelor-level (not specified)

Tools

Verilog simulators

Linting tools

CDC checkers

Synthesis tools

Formal verification

Job description

Silicon One is Cisco's leading hardware team responsible for cutting-edge AI-era silicon powering core Switching, Routing, and Wireless products. This role focuses on high-quality structural/functional test, diagnostic features, IP development, and robust test access within Cisco’s scalable silicon architecture.

Join a global, collaborative team that drives performance, security, and innovation across Cisco’s silicon platforms, working closely with RTL and backend design groups to deliver