Senior ASIC DFT Engineering Lead

Cisco Systems, Inc; San Jose (CA); Presencial; USD 187 000 - 268 000; Tempo integral

Resumo da oferta

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test within the Silicon One team. You will work with Front-end RTL and backend physical design teams to define DFT requirements early in the design cycle and help craft next‑generation networking chips.

You will drive DFT and quality processes through the implementation flow and post-silicon validation, with exposure to signoff activities and collaboration with ATE engineers on pattern translation.

Qualificações

• Bachelor’s degree in Electrical or Computer Engineering with 8+ years experience, or Master’s with 6+ years, or PhD with 3 years.
• Experience with ATPG and EDA tools such as TestMax, Tetramax or Tessent.
• Experience with gate-level simulation and timing-based simulations using SDF, debugging with VCS.
• Post-silicon validation and debug experience.
• Experience with scan insertion.

Responsabilidades

• Collaborate with Front-end RTL and backend physical design teams to drive DFT requirements early in design.
• Contribute to developing next-generation networking chips and DFT/quality processes across the implementation flow.
• Lead post-silicon validation activities and assist with physical design signoff as needed.
• Coordinate with ATE engineers on pattern translation and validation.

Conhecimentos

ATPG & EDA tools

Gate-level simulation

Post-silicon validation

Scan insertion

RTL/Physical design collaboration

Formação académica

Bachelor’s degree in Electrical or Computer engineering

Master’s degree in Electrical Engineering or Computer Engineering

PhD in Electrical Engineering or Computer Engineering

Ferramentas

TestMax

Tetramax

Tessent

Descrição da oferta de emprego

Cisco Systems, Inc. is seeking an ASIC Implementation Technical Lead focused on Design-for-Test within the Silicon One team. You will work with Front-end RTL and backend physical design teams to define DFT requirements early in the design cycle and help craft next‑generation networking chips.

You will drive DFT and quality processes through the implementation flow and post-silicon validation, with exposure to signoff activities and collaboration with ATE engineers on pattern translation.